1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Cross-Module Referencing (XMR) in HDL Code 1.9. Using force Statements in HDL Code 1.10. Recommended HDL Coding Styles Revision History
22.214.171.124. Use Synchronous Memory Blocks 126.96.36.199. Avoid Unsupported Reset and Control Conditions 188.8.131.52. Check Read-During-Write Behavior 184.108.40.206. Controlling RAM Inference and Implementation 220.127.116.11. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 18.104.22.168. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 22.214.171.124. Simple Dual-Port, Dual-Clock Synchronous RAM 126.96.36.199. True Dual-Port Synchronous RAM 188.8.131.52. Mixed-Width Dual-Port RAM 184.108.40.206. RAM with Byte-Enable Signals 220.127.116.11. Specifying Initial Memory Contents at Power-Up
18.104.22.168. If Performance is Important, Optimize for Speed 22.214.171.124. Use Separate CRC Blocks Instead of Cascaded Stages 126.96.36.199. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 188.8.131.52. Take Advantage of Latency if Available 184.108.40.206. Save Power by Disabling CRC Blocks When Not in Use 220.127.116.11. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
18.104.22.168.1. Creating Design Assistant Waivers
To create a design rule waiver, follow these steps:
- Run one or more stages of the Compiler to generate Design Assistant reports for the rules that you enable for your design.
- In the Design Assistant report, right-click one or more rule violations, or right-click an entire rule category in the rule summary list, and then click Design Assistant Waiver. The Design Assistant Waiver dialog box opens preset with values from your violation selection.
Figure 42. Right-Click Rule Violation in Report to Create Waiver for Violation
- Modify any of the default Violation conditions that define when the waiver applies. The default settings are the most descriptive, using all applicable fields. The comparison operator is always == (equal to) by default for all conditions. Refer to Design Assistant Waiver Dialog Box for all available options.
- Click the X button to delete a sub-condition and simplify the query. Click Add Condition to add a violation sub-condition.
- For waiver identification and audit tracking, optionally specify the waiver Owner name, a descriptive Tag, and a text Description.
Figure 43. Design Assistant Waiver Dialog Box
- To preview the waived violations, click the Preview button. The Waived violations by the waiver list shows the waived rule violations during the next Design Assistant run. When you create a waiver after running Design Assistant, the newly added waiver specifies To be Waived in the Waived column. For any waivers that you delete, the Waiver column specifies Y + To be unwaived.
- When waiver definition is complete, click OK to apply the waiver the next time you run Design Assistant. Design Assistant does not check for compliance with the rules that match waiver conditions, nor report results for the rules you waive. The Design Assistant reports indicate waived violations following compilation.
Figure 44. Applied Waiver Reported in Compilation Report
The report's Waived column specifies Y (for yes) for waived violations.
Design Assistant saves the rule waiver to a da_drc.dawf file in the project directory.
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