184.108.40.206. Controlling RAM Inference and Implementation
To direct the Intel® Quartus® Prime software to infer RAM blocks globally for all sizes, enable the Allow Any RAM Size for Recognition option in the Advanced Analysis & Synthesis Settings dialog box (Assignments > Settings > Compiler Settings > Synthesis Settings (Advanced)).
Alternatively, use the ramstyle RTL attribute to specify how an inferred RAM is implemented, including the type of memory block or the use of regular logic instead of a dedicated memory block. Intel® Quartus® Prime synthesis does not map inferred memory into MLABs unless the HDL code specifies the appropriate ramstyle attribute, although the Fitter may map some memories to MLABs.
(* ramstyle = "mlab" *) my_shift_reg
set_instance_assignment -name RAMSTYLE_ATTRIBUTE LOGIC -to ram. This attribute controls the implementation of an inferred memory. Apply the attribute to a variable declaration that infers a RAM, ROM, or shift-register. Legal values are: "M9K", "M10K", "M20K", "M144K", "MLAB, "no_rw_check", "logic"
You can also specify the maximum depth of memory blocks for RAM or ROM inference in RTL. Specify the max_depth synthesis attribute to the declaration of a variable that represents a RAM or ROM in your design file. For example:
// Limit the depth of the memory blocks implement "ram" to 512 // This forces the Intel® Quartus® Prime software to use two M512 blocks instead of one M4K block to implement this RAM (* max_depth = 512 *) reg [7:0] ram[0:1023];
In addition, you can specify the no_ram synthesis attribute to prevent RAM inference on a specific array. For example:
(* no_ram *) logic [11:0] my_array [0:12];
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