smmu_tcu Address Map

TCU Registers


Module Instance	Base Address	End Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x1603FFFF`


Register	Offset	Width	Access	Reset Value	Description
`SMMU_IDR0`	`0x0`	`32`	`RO`	`0x080F7E3F`	SMMU_IDR0
`SMMU_IDR1`	`0x4`	`32`	`RO`	`0x0E739D18`	SMMU_IDR1
`SMMU_IDR2`	`0x8`	`32`	`RO`	`0x00000000`	SMMU_IDR2
`SMMU_IDR3`	`0xC`	`32`	`RO`	`0x0000003C`	SMMU_IDR3
`SMMU_IDR5`	`0x14`	`32`	`RO`	`0x00400075`	SMMU_IDR5
`SMMU_IIDR`	`0x18`	`32`	`RO`	`0x4832243B`	SMMU_IIDR
`SMMU_AIDR`	`0x1C`	`32`	`RO`	`0x00000001`	SMMU_AIDR
`SMMU_CR0`	`0x20`	`32`	`RO`	`0x00000000`	SMMU_CR0
`SMMU_CR0ACK`	`0x24`	`32`	`RO`	`0x00000000`	SMMU_CR0ACK
`SMMU_CR1`	`0x28`	`32`	`RO`	`0x00000000`	SMMU_CR1
`SMMU_CR2`	`0x2C`	`32`	`RO`	`0x00000004`	SMMU_CR2
`SMMU_GBPA`	`0x44`	`32`	`RW`	`0x00000000`	SMMU_GBPA
`SMMU_IRQ_CTRL`	`0x50`	`32`	`RO`	`0x00000000`	SMMU_IRQ_CTRL
`SMMU_IRQ_CTRLACK`	`0x54`	`32`	`RO`	`0x00000000`	SMMU_IRQ_CTRLACK
`SMMU_GERROR`	`0x60`	`32`	`RO`	`0x00000000`	SMMU_GERROR
`SMMU_GERRORN`	`0x64`	`32`	`RO`	`0x00000000`	SMMU_GERRORN
`SMMU_GERROR_IRQ_CFG0_LO`	`0x68`	`32`	`RW`	`0x00000000`	SMMU_GERROR_IRQ_CFG0 (Least Significant 32-bits)
`SMMU_GERROR_IRQ_CFG0_HI`	`0x6C`	`32`	`RO`	`0x00000000`	SMMU_GERROR_IRQ_CFG0 (Most Significant 32-bits)
`SMMU_GERROR_IRQ_CFG1`	`0x70`	`32`	`RW`	`0x00000000`	SMMU_GERROR_IRQ_CFG1
`SMMU_GERROR_IRQ_CFG2`	`0x74`	`32`	`RO`	`0x00000000`	SMMU_GERROR_IRQ_CFG2
`SMMU_STRTAB_BASE_LO`	`0x80`	`32`	`RW`	`0x00000000`	SMMU_STRTAB_BASE (Least Significant 32-bits)
`SMMU_STRTAB_BASE_HI`	`0x84`	`32`	`RO`	`0x00000000`	SMMU_STRTAB_BASE (Most Significant 32-bits)
`SMMU_STRTAB_BASE_CFG`	`0x88`	`32`	`RO`	`0x00000000`	SMMU_STRTAB_BASE_CFG
`SMMU_CMDQ_BASE_LO`	`0x90`	`32`	`RW`	`0x00000000`	SMMU_CMDQ_BASE (Least Significant 32-bits)
`SMMU_CMDQ_BASE_HI`	`0x94`	`32`	`RO`	`0x00000000`	SMMU_CMDQ_BASE (Most Significant 32-bits)
`SMMU_CMDQ_PROD`	`0x98`	`32`	`RO`	`0x00000000`	SMMU_CMDQ_PROD
`SMMU_CMDQ_CONS`	`0x9C`	`32`	`RO`	`0x00000000`	SMMU_CMDQ_CONS
`SMMU_EVENTQ_BASE_LO`	`0xA0`	`32`	`RW`	`0x00000000`	SMMU_EVENTQ_BASE (Least Significant 32-bits)
`SMMU_EVENTQ_BASE_HI`	`0xA4`	`32`	`RO`	`0x00000000`	SMMU_EVENTQ_BASE (Most Significant 32-bits)
`SMMU_EVENTQ_IRQ_CFG0_LO`	`0xB0`	`32`	`RW`	`0x00000000`	SMMU_EVENTQ_IRQ_CFG0 (Least Significant 32-bits)
`SMMU_EVENTQ_IRQ_CFG0_HI`	`0xB4`	`32`	`RO`	`0x00000000`	SMMU_EVENTQ_IRQ_CFG0 (Most Significant 32-bits)
`SMMU_EVENTQ_IRQ_CFG1`	`0xB8`	`32`	`RW`	`0x00000000`	SMMU_EVENTQ_IRQ_CFG1
`SMMU_EVENTQ_IRQ_CFG2`	`0xBC`	`32`	`RO`	`0x00000000`	SMMU_EVENTQ_IRQ_CFG2
`SMMU_PRIQ_BASE_LO`	`0xC0`	`32`	`RW`	`0x00000000`	SMMU_PRIQ_BASE (Least Significant 32-bits)
`SMMU_PRIQ_BASE_HI`	`0xC4`	`32`	`RO`	`0x00000000`	SMMU_PRIQ_BASE (Most Significant 32-bits)
`SMMU_PRIQ_IRQ_CFG0_LO`	`0xD0`	`32`	`RW`	`0x00000000`	SMMU_PRIQ_IRQ_CFG0 (Least Significant 32-bits)
`SMMU_PRIQ_IRQ_CFG0_HI`	`0xD4`	`32`	`RO`	`0x00000000`	SMMU_PRIQ_IRQ_CFG0 (Most Significant 32-bits)
`SMMU_PRIQ_IRQ_CFG1`	`0xD8`	`32`	`RW`	`0x00000000`	SMMU_PRIQ_IRQ_CFG1
`SMMU_PRIQ_IRQ_CFG2`	`0xDC`	`32`	`RW`	`0x00000000`	SMMU_PRIQ_IRQ_CFG2
`SMMU_PIDR4`	`0xFD0`	`32`	`RO`	`0x00000004`	Peripheral ID4
`SMMU_PIDR5`	`0xFD4`	`32`	`RO`	`0x00000000`	Peripheral ID5
`SMMU_PIDR6`	`0xFD8`	`32`	`RO`	`0x00000000`	Peripheral ID6
`SMMU_PIDR7`	`0xFDC`	`32`	`RO`	`0x00000000`	Peripheral ID7
`SMMU_PIDR0`	`0xFE0`	`32`	`RO`	`0x00000083`	Peripheral ID0
`SMMU_PIDR1`	`0xFE4`	`32`	`RO`	`0x000000B4`	Peripheral ID1
`SMMU_PIDR2`	`0xFE8`	`32`	`RO`	`0x0000002B`	Peripheral ID2
`SMMU_PIDR3`	`0xFEC`	`32`	`RO`	`0x00000020`	Peripheral ID3
`SMMU_CIDR0`	`0xFF0`	`32`	`RO`	`0x0000000D`	Component ID0
`SMMU_CIDR1`	`0xFF4`	`32`	`RO`	`0x000000F0`	Component ID1
`SMMU_CIDR2`	`0xFF8`	`32`	`RO`	`0x00000005`	Component ID2
`SMMU_CIDR3`	`0xFFC`	`32`	`RO`	`0x000000B1`	Component ID3
`SMMU_PMCG_EVTYPER0`	`0x2400`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVTYPER0
`SMMU_PMCG_EVTYPER1`	`0x2404`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVTYPER1
`SMMU_PMCG_EVTYPER2`	`0x2408`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVTYPER2
`SMMU_PMCG_EVTYPER3`	`0x240C`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVTYPER3
`SMMU_PMCG_SMR0`	`0x2A00`	`32`	`RO`	`0x00000000`	SMMU_PMCG_SMR0
`SMMU_PMCG_CNTENSET0`	`0x2C00`	`32`	`RO`	`0x00000000`	SMMU_PMCG_CNTENSET0
`SMMU_PMCG_CNTENCLR0`	`0x2C20`	`32`	`RO`	`0x00000000`	SMMU_PMCG_CNTENCLR0
`SMMU_PMCG_INTENSET0`	`0x2C40`	`32`	`RO`	`0x00000000`	SMMU_PMCG_INTENSET0
`SMMU_PMCG_INTENCLR0`	`0x2C60`	`32`	`RO`	`0x00000000`	SMMU_PMCG_INTENCLR0
`SMMU_PMCG_SCR`	`0x2DF8`	`32`	`RW`	`0x80000002`	SMMU_PMCG_SCR
`SMMU_PMCG_CFGR`	`0x2E00`	`32`	`RO`	`0x00D01F03`	SMMU_PMCG_CFGR
`SMMU_PMCG_CR`	`0x2E04`	`32`	`RO`	`0x00000000`	SMMU_PMCG_CR
`SMMU_PMCG_CEID0_LO`	`0x2E20`	`32`	`RO`	`0x0000007F`	SMMU_PMCG_CEID0 (Least Significant 32-bits)
`SMMU_PMCG_CEID0_HI`	`0x2E24`	`32`	`RO`	`0x00000000`	SMMU_PMCG_CEID0 (Most Significant 32-bits)
`SMMU_PMCG_CEID1_LO`	`0x2E28`	`32`	`RO`	`0x00000000`	SMMU_PMCG_CEID1 (Least Significant 32-bits)
`SMMU_PMCG_CEID1_HI`	`0x2E2C`	`32`	`RO`	`0x00000000`	SMMU_PMCG_CEID1 (Most Significant 32-bits)
`SMMU_PMCG_IRQ_CTRL`	`0x2E50`	`32`	`RO`	`0x00000000`	SMMU_PMCG_IRQ_CTRL
`SMMU_PMCG_IRQ_CTRLACK`	`0x2E54`	`32`	`RO`	`0x00000000`	SMMU_PMCG_IRQ_CTRLACK
`SMMU_PMCG_AIDR`	`0x2E70`	`32`	`RO`	`0x00000001`	SMMU_PMCG_AIDR
`SMMU_PMCG_PMAUTHSTATUS`	`0x2FB8`	`32`	`RO`	`0x00000000`	PMU Authentication Status Register
`SMMU_PMCG_PMDEVARCH`	`0x2FBC`	`32`	`RO`	`0x47702A56`	PMU Device Architecture Register
`SMMU_PMCG_PMDEVTYPE`	`0x2FCC`	`32`	`RO`	`0x00000056`	PMU Device Type Register
`SMMU_PMCG_PIDR4`	`0x2FD0`	`32`	`RO`	`0x00000004`	PMU Peripheral ID4
`SMMU_PMCG_PIDR5`	`0x2FD4`	`32`	`RO`	`0x00000000`	PMU Peripheral ID5
`SMMU_PMCG_PIDR6`	`0x2FD8`	`32`	`RO`	`0x00000000`	PMU Peripheral ID6
`SMMU_PMCG_PIDR7`	`0x2FDC`	`32`	`RO`	`0x00000000`	PMU Peripheral ID7
`SMMU_PMCG_PIDR0`	`0x2FE0`	`32`	`RO`	`0x00000083`	PMU Peripheral ID0
`SMMU_PMCG_PIDR1`	`0x2FE4`	`32`	`RO`	`0x000000B4`	PMU Peripheral ID1
`SMMU_PMCG_PIDR2`	`0x2FE8`	`32`	`RO`	`0x0000002B`	PMU Peripheral ID2
`SMMU_PMCG_PIDR3`	`0x2FEC`	`32`	`RO`	`0x00000020`	PMU Peripheral ID3
`SMMU_PMCG_CIDR0`	`0x2FF0`	`32`	`RO`	`0x0000000D`	PMU Component ID0
`SMMU_PMCG_CIDR1`	`0x2FF4`	`32`	`RO`	`0x00000090`	PMU Component ID1
`SMMU_PMCG_CIDR2`	`0x2FF8`	`32`	`RO`	`0x00000005`	PMU Component ID2
`SMMU_PMCG_CIDR3`	`0x2FFC`	`32`	`RO`	`0x000000B1`	PMU Component ID3
`SMMU_S_IDR0`	`0x8000`	`32`	`RO`	`0x00002000`	SMMU_S_IDR0
`SMMU_S_IDR1`	`0x8004`	`32`	`RO`	`0x80000018`	SMMU_S_IDR1
`SMMU_S_IDR3`	`0x800C`	`32`	`RO`	`0x00000040`	SMMU_S_IDR3
`SMMU_S_CR0`	`0x8020`	`32`	`RO`	`0x00000000`	SMMU_S_CR0
`SMMU_S_CR0ACK`	`0x8024`	`32`	`RO`	`0x00000000`	SMMU_S_CR0ACK
`SMMU_S_CR1`	`0x8028`	`32`	`RO`	`0x00000000`	SMMU_S_CR1
`SMMU_S_CR2`	`0x802C`	`32`	`RO`	`0x00000004`	SMMU_S_CR2
`SMMU_S_INIT`	`0x803C`	`32`	`RO`	`0x00000000`	SMMU_S_INIT
`SMMU_S_GBPA`	`0x8044`	`32`	`RW`	`0x00000000`	SMMU_S_GBPA
`SMMU_S_IRQ_CTRL`	`0x8050`	`32`	`RO`	`0x00000000`	SMMU_S_IRQ_CTRL
`SMMU_S_IRQ_CTRLACK`	`0x8054`	`32`	`RO`	`0x00000000`	SMMU_S_IRQ_CTRLACK
`SMMU_S_GERROR`	`0x8060`	`32`	`RO`	`0x00000000`	SMMU_S_GERROR
`SMMU_S_GERRORN`	`0x8064`	`32`	`RO`	`0x00000000`	SMMU_S_GERRORN
`SMMU_S_GERROR_IRQ_CFG0_LO`	`0x8068`	`32`	`RW`	`0x00000000`	SMMU_S_GERROR_IRQ_CFG0 (Least Significant 32-bits)
`SMMU_S_GERROR_IRQ_CFG0_HI`	`0x806C`	`32`	`RO`	`0x00000000`	SMMU_S_GERROR_IRQ_CFG0 (Most Significant 32-bits)
`SMMU_S_GERROR_IRQ_CFG1`	`0x8070`	`32`	`RW`	`0x00000000`	SMMU_S_GERROR_IRQ_CFG1
`SMMU_S_GERROR_IRQ_CFG2`	`0x8074`	`32`	`RO`	`0x00000000`	SMMU_S_GERROR_IRQ_CFG2
`SMMU_S_STRTAB_BASE_LO`	`0x8080`	`32`	`RW`	`0x00000000`	SMMU_S_STRTAB_BASE (Least Significant 32-bits)
`SMMU_S_STRTAB_BASE_HI`	`0x8084`	`32`	`RO`	`0x00000000`	SMMU_S_STRTAB_BASE (Most Significant 32-bits)
`SMMU_S_STRTAB_BASE_CFG`	`0x8088`	`32`	`RO`	`0x00000000`	SMMU_S_STRTAB_BASE_CFG
`SMMU_S_CMDQ_BASE_LO`	`0x8090`	`32`	`RW`	`0x00000000`	SMMU_S_CMDQ_BASE (Least Significant 32-bits)
`SMMU_S_CMDQ_BASE_HI`	`0x8094`	`32`	`RO`	`0x00000000`	SMMU_S_CMDQ_BASE (Most Significant 32-bits)
`SMMU_S_CMDQ_PROD`	`0x8098`	`32`	`RO`	`0x00000000`	SMMU_S_CMDQ_PROD
`SMMU_S_CMDQ_CONS`	`0x809C`	`32`	`RO`	`0x00000000`	SMMU_S_CMDQ_CONS
`SMMU_S_EVENTQ_BASE_LO`	`0x80A0`	`32`	`RW`	`0x00000000`	SMMU_S_EVENTQ_BASE (Least Significant 32-bits)
`SMMU_S_EVENTQ_BASE_HI`	`0x80A4`	`32`	`RO`	`0x00000000`	SMMU_S_EVENTQ_BASE (Most Significant 32-bits)
`SMMU_S_EVENTQ_PROD`	`0x80A8`	`32`	`RW`	`0x00000000`	SMMU_S_EVENTQ_PROD
`SMMU_S_EVENTQ_CONS`	`0x80AC`	`32`	`RW`	`0x00000000`	SMMU_S_EVENTQ_CONS
`SMMU_S_EVENTQ_IRQ_CFG0_LO`	`0x80B0`	`32`	`RW`	`0x00000000`	SMMU_S_EVENTQ_IRQ_CFG0 (Least Significant 32-bits)
`SMMU_S_EVENTQ_IRQ_CFG0_HI`	`0x80B4`	`32`	`RO`	`0x00000000`	SMMU_S_EVENTQ_IRQ_CFG0 (Most Significant 32-bits)
`SMMU_S_EVENTQ_IRQ_CFG1`	`0x80B8`	`32`	`RW`	`0x00000000`	SMMU_S_EVENTQ_IRQ_CFG1
`SMMU_S_EVENTQ_IRQ_CFG2`	`0x80BC`	`32`	`RO`	`0x00000000`	SMMU_S_EVENTQ_IRQ_CFG2
`TCU_CTRL`	`0x8E00`	`32`	`RW`	`0x00000000`	TCU Control Register
`TCU_QOS`	`0x8E04`	`32`	`RO`	`0x00000000`	TCU Quality of Service Register
`TCU_CFG`	`0x8E08`	`32`	`RO`	`0x00000400`	TCU Configuration Information Register
`TCU_STATUS`	`0x8E10`	`32`	`RO`	`0x00000000`	TCU Status Information Register
`TCU_SCR`	`0x8E18`	`32`	`RO`	`0x00000000`	TCU Secure Control Register
`TCU_ERRFR_LO`	`0x8E80`	`32`	`RO`	`0x00000081`	TCU Error Feature Register (Least Significant 32-bits)
`TCU_ERRFR_HI`	`0x8E84`	`32`	`RO`	`0x00000000`	TCU Error Feature Register (Most Significant 32-bits)
`TCU_ERRCTLR_LO`	`0x8E88`	`32`	`RO`	`0x00000008`	TCU Error Control Register (Least Significant 32-bits)
`TCU_ERRCTLR_HI`	`0x8E8C`	`32`	`RO`	`0x00000000`	TCU Error Control Register (Most Significant 32-bits)
`TCU_ERRSTATUS_LO`	`0x8E90`	`32`	`RO`	`0x00000000`	TCU Error Status Register (Least Significant 32-bits)
`TCU_ERRSTATUS_HI`	`0x8E94`	`32`	`RO`	`0x00000000`	TCU Error Status Register (Most Significant 32-bits)
`TCU_ERRGEN_LO`	`0x8EC0`	`32`	`RO`	`0x00000000`	TCU Error Generation Register (Least Significant 32-bits)
`TCU_ERRGEN_HI`	`0x8EC4`	`32`	`RO`	`0x00000000`	TCU Error Generation Register (Most Significant 32-bits)
`TCU_NODE_CTRL0`	`0x9000`	`32`	`RO`	`0x00000000`	TCU Node Control Register0
`TCU_NODE_CTRL1`	`0x9004`	`32`	`RO`	`0x00000000`	TCU Node Control Register1
`TCU_NODE_CTRL2`	`0x9008`	`32`	`RO`	`0x00000000`	TCU Node Control Register2
`TCU_NODE_CTRL3`	`0x900C`	`32`	`RO`	`0x00000000`	TCU Node Control Register3
`TCU_NODE_CTRL4`	`0x9010`	`32`	`RO`	`0x00000000`	TCU Node Control Register4
`TCU_NODE_CTRL5`	`0x9014`	`32`	`RO`	`0x00000000`	TCU Node Control Register5
`TCU_NODE_CTRL6`	`0x9018`	`32`	`RO`	`0x00000000`	TCU Node Control Register6
`TCU_NODE_CTRL7`	`0x901C`	`32`	`RO`	`0x00000000`	TCU Node Control Register7
`TCU_NODE_CTRL8`	`0x9020`	`32`	`RO`	`0x00000000`	TCU Node Control Register8
`TCU_NODE_CTRL9`	`0x9024`	`32`	`RO`	`0x00000000`	TCU Node Control Register9
`TCU_NODE_CTRL10`	`0x9028`	`32`	`RO`	`0x00000000`	TCU Node Control Register10
`TCU_NODE_CTRL11`	`0x902C`	`32`	`RO`	`0x00000000`	TCU Node Control Register11
`TCU_NODE_CTRL12`	`0x9030`	`32`	`RO`	`0x00000000`	TCU Node Control Register12
`TCU_NODE_CTRL13`	`0x9034`	`32`	`RO`	`0x00000000`	TCU Node Control Register13
`TCU_NODE_CTRL14`	`0x9038`	`32`	`RO`	`0x00000000`	TCU Node Control Register14
`TCU_NODE_CTRL15`	`0x903C`	`32`	`RO`	`0x00000000`	TCU Node Control Register15
`TCU_NODE_CTRL16`	`0x9040`	`32`	`RO`	`0x00000000`	TCU Node Control Register16
`TCU_NODE_CTRL17`	`0x9044`	`32`	`RO`	`0x00000000`	TCU Node Control Register17
`TCU_NODE_CTRL18`	`0x9048`	`32`	`RO`	`0x00000000`	TCU Node Control Register18
`TCU_NODE_CTRL19`	`0x904C`	`32`	`RO`	`0x00000000`	TCU Node Control Register19
`TCU_NODE_CTRL20`	`0x9050`	`32`	`RO`	`0x00000000`	TCU Node Control Register20
`TCU_NODE_CTRL21`	`0x9054`	`32`	`RO`	`0x00000000`	TCU Node Control Register21
`TCU_NODE_CTRL22`	`0x9058`	`32`	`RO`	`0x00000000`	TCU Node Control Register22
`TCU_NODE_CTRL23`	`0x905C`	`32`	`RO`	`0x00000000`	TCU Node Control Register23
`TCU_NODE_CTRL24`	`0x9060`	`32`	`RO`	`0x00000000`	TCU Node Control Register24
`TCU_NODE_CTRL25`	`0x9064`	`32`	`RO`	`0x00000000`	TCU Node Control Register25
`TCU_NODE_CTRL26`	`0x9068`	`32`	`RO`	`0x00000000`	TCU Node Control Register26
`TCU_NODE_CTRL27`	`0x906C`	`32`	`RO`	`0x00000000`	TCU Node Control Register27
`TCU_NODE_CTRL28`	`0x9070`	`32`	`RO`	`0x00000000`	TCU Node Control Register28
`TCU_NODE_CTRL29`	`0x9074`	`32`	`RO`	`0x00000000`	TCU Node Control Register29
`TCU_NODE_CTRL30`	`0x9078`	`32`	`RO`	`0x00000000`	TCU Node Control Register30
`TCU_NODE_CTRL31`	`0x907C`	`32`	`RO`	`0x00000000`	TCU Node Control Register31
`TCU_NODE_CTRL32`	`0x9080`	`32`	`RO`	`0x00000000`	TCU Node Control Register32
`TCU_NODE_CTRL33`	`0x9084`	`32`	`RO`	`0x00000000`	TCU Node Control Register33
`TCU_NODE_CTRL34`	`0x9088`	`32`	`RO`	`0x00000000`	TCU Node Control Register34
`TCU_NODE_CTRL35`	`0x908C`	`32`	`RO`	`0x00000000`	TCU Node Control Register35
`TCU_NODE_CTRL36`	`0x9090`	`32`	`RO`	`0x00000000`	TCU Node Control Register36
`TCU_NODE_CTRL37`	`0x9094`	`32`	`RO`	`0x00000000`	TCU Node Control Register37
`TCU_NODE_CTRL38`	`0x9098`	`32`	`RO`	`0x00000000`	TCU Node Control Register38
`TCU_NODE_CTRL39`	`0x909C`	`32`	`RO`	`0x00000000`	TCU Node Control Register39
`TCU_NODE_CTRL40`	`0x90A0`	`32`	`RO`	`0x00000000`	TCU Node Control Register40
`TCU_NODE_CTRL41`	`0x90A4`	`32`	`RO`	`0x00000000`	TCU Node Control Register41
`TCU_NODE_CTRL42`	`0x90A8`	`32`	`RO`	`0x00000000`	TCU Node Control Register42
`TCU_NODE_CTRL43`	`0x90AC`	`32`	`RO`	`0x00000000`	TCU Node Control Register43
`TCU_NODE_CTRL44`	`0x90B0`	`32`	`RO`	`0x00000000`	TCU Node Control Register44
`TCU_NODE_CTRL45`	`0x90B4`	`32`	`RO`	`0x00000000`	TCU Node Control Register45
`TCU_NODE_CTRL46`	`0x90B8`	`32`	`RO`	`0x00000000`	TCU Node Control Register46
`TCU_NODE_CTRL47`	`0x90BC`	`32`	`RO`	`0x00000000`	TCU Node Control Register47
`TCU_NODE_CTRL48`	`0x90C0`	`32`	`RO`	`0x00000000`	TCU Node Control Register48
`TCU_NODE_CTRL49`	`0x90C4`	`32`	`RO`	`0x00000000`	TCU Node Control Register49
`TCU_NODE_CTRL50`	`0x90C8`	`32`	`RO`	`0x00000000`	TCU Node Control Register50
`TCU_NODE_CTRL51`	`0x90CC`	`32`	`RO`	`0x00000000`	TCU Node Control Register51
`TCU_NODE_CTRL52`	`0x90D0`	`32`	`RO`	`0x00000000`	TCU Node Control Register52
`TCU_NODE_CTRL53`	`0x90D4`	`32`	`RO`	`0x00000000`	TCU Node Control Register53
`TCU_NODE_CTRL54`	`0x90D8`	`32`	`RO`	`0x00000000`	TCU Node Control Register54
`TCU_NODE_CTRL55`	`0x90DC`	`32`	`RO`	`0x00000000`	TCU Node Control Register55
`TCU_NODE_CTRL56`	`0x90E0`	`32`	`RO`	`0x00000000`	TCU Node Control Register56
`TCU_NODE_CTRL57`	`0x90E4`	`32`	`RO`	`0x00000000`	TCU Node Control Register57
`TCU_NODE_CTRL58`	`0x90E8`	`32`	`RO`	`0x00000000`	TCU Node Control Register58
`TCU_NODE_CTRL59`	`0x90EC`	`32`	`RO`	`0x00000000`	TCU Node Control Register59
`TCU_NODE_CTRL60`	`0x90F0`	`32`	`RO`	`0x00000000`	TCU Node Control Register60
`TCU_NODE_CTRL61`	`0x90F4`	`32`	`RO`	`0x00000000`	TCU Node Control Register61
`TCU_NODE_STATUS0`	`0x9400`	`32`	`RO`	`0x00000000`	TCU Node Status Register0
`TCU_NODE_STATUS1`	`0x9404`	`32`	`RO`	`0x00000000`	TCU Node Status Register1
`TCU_NODE_STATUS2`	`0x9408`	`32`	`RO`	`0x00000000`	TCU Node Status Register2
`TCU_NODE_STATUS3`	`0x940C`	`32`	`RO`	`0x00000000`	TCU Node Status Register3
`TCU_NODE_STATUS4`	`0x9410`	`32`	`RO`	`0x00000000`	TCU Node Status Register4
`TCU_NODE_STATUS5`	`0x9414`	`32`	`RO`	`0x00000000`	TCU Node Status Register5
`TCU_NODE_STATUS6`	`0x9418`	`32`	`RO`	`0x00000000`	TCU Node Status Register6
`TCU_NODE_STATUS7`	`0x941C`	`32`	`RO`	`0x00000000`	TCU Node Status Register7
`TCU_NODE_STATUS8`	`0x9420`	`32`	`RO`	`0x00000000`	TCU Node Status Register8
`TCU_NODE_STATUS9`	`0x9424`	`32`	`RO`	`0x00000000`	TCU Node Status Register9
`TCU_NODE_STATUS10`	`0x9428`	`32`	`RO`	`0x00000000`	TCU Node Status Register10
`TCU_NODE_STATUS11`	`0x942C`	`32`	`RO`	`0x00000000`	TCU Node Status Register11
`TCU_NODE_STATUS12`	`0x9430`	`32`	`RO`	`0x00000000`	TCU Node Status Register12
`TCU_NODE_STATUS13`	`0x9434`	`32`	`RO`	`0x00000000`	TCU Node Status Register13
`TCU_NODE_STATUS14`	`0x9438`	`32`	`RO`	`0x00000000`	TCU Node Status Register14
`TCU_NODE_STATUS15`	`0x943C`	`32`	`RO`	`0x00000000`	TCU Node Status Register15
`TCU_NODE_STATUS16`	`0x9440`	`32`	`RO`	`0x00000000`	TCU Node Status Register16
`TCU_NODE_STATUS17`	`0x9444`	`32`	`RO`	`0x00000000`	TCU Node Status Register17
`TCU_NODE_STATUS18`	`0x9448`	`32`	`RO`	`0x00000000`	TCU Node Status Register18
`TCU_NODE_STATUS19`	`0x944C`	`32`	`RO`	`0x00000000`	TCU Node Status Register19
`TCU_NODE_STATUS20`	`0x9450`	`32`	`RO`	`0x00000000`	TCU Node Status Register20
`TCU_NODE_STATUS21`	`0x9454`	`32`	`RO`	`0x00000000`	TCU Node Status Register21
`TCU_NODE_STATUS22`	`0x9458`	`32`	`RO`	`0x00000000`	TCU Node Status Register22
`TCU_NODE_STATUS23`	`0x945C`	`32`	`RO`	`0x00000000`	TCU Node Status Register23
`TCU_NODE_STATUS24`	`0x9460`	`32`	`RO`	`0x00000000`	TCU Node Status Register24
`TCU_NODE_STATUS25`	`0x9464`	`32`	`RO`	`0x00000000`	TCU Node Status Register25
`TCU_NODE_STATUS26`	`0x9468`	`32`	`RO`	`0x00000000`	TCU Node Status Register26
`TCU_NODE_STATUS27`	`0x946C`	`32`	`RO`	`0x00000000`	TCU Node Status Register27
`TCU_NODE_STATUS28`	`0x9470`	`32`	`RO`	`0x00000000`	TCU Node Status Register28
`TCU_NODE_STATUS29`	`0x9474`	`32`	`RO`	`0x00000000`	TCU Node Status Register29
`TCU_NODE_STATUS30`	`0x9478`	`32`	`RO`	`0x00000000`	TCU Node Status Register30
`TCU_NODE_STATUS31`	`0x947C`	`32`	`RO`	`0x00000000`	TCU Node Status Register31
`TCU_NODE_STATUS32`	`0x9480`	`32`	`RO`	`0x00000000`	TCU Node Status Register32
`TCU_NODE_STATUS33`	`0x9484`	`32`	`RO`	`0x00000000`	TCU Node Status Register33
`TCU_NODE_STATUS34`	`0x9488`	`32`	`RO`	`0x00000000`	TCU Node Status Register34
`TCU_NODE_STATUS35`	`0x948C`	`32`	`RO`	`0x00000000`	TCU Node Status Register35
`TCU_NODE_STATUS36`	`0x9490`	`32`	`RO`	`0x00000000`	TCU Node Status Register36
`TCU_NODE_STATUS37`	`0x9494`	`32`	`RO`	`0x00000000`	TCU Node Status Register37
`TCU_NODE_STATUS38`	`0x9498`	`32`	`RO`	`0x00000000`	TCU Node Status Register38
`TCU_NODE_STATUS39`	`0x949C`	`32`	`RO`	`0x00000000`	TCU Node Status Register39
`TCU_NODE_STATUS40`	`0x94A0`	`32`	`RO`	`0x00000000`	TCU Node Status Register40
`TCU_NODE_STATUS41`	`0x94A4`	`32`	`RO`	`0x00000000`	TCU Node Status Register41
`TCU_NODE_STATUS42`	`0x94A8`	`32`	`RO`	`0x00000000`	TCU Node Status Register42
`TCU_NODE_STATUS43`	`0x94AC`	`32`	`RO`	`0x00000000`	TCU Node Status Register43
`TCU_NODE_STATUS44`	`0x94B0`	`32`	`RO`	`0x00000000`	TCU Node Status Register44
`TCU_NODE_STATUS45`	`0x94B4`	`32`	`RO`	`0x00000000`	TCU Node Status Register45
`TCU_NODE_STATUS46`	`0x94B8`	`32`	`RO`	`0x00000000`	TCU Node Status Register46
`TCU_NODE_STATUS47`	`0x94BC`	`32`	`RO`	`0x00000000`	TCU Node Status Register47
`TCU_NODE_STATUS48`	`0x94C0`	`32`	`RO`	`0x00000000`	TCU Node Status Register48
`TCU_NODE_STATUS49`	`0x94C4`	`32`	`RO`	`0x00000000`	TCU Node Status Register49
`TCU_NODE_STATUS50`	`0x94C8`	`32`	`RO`	`0x00000000`	TCU Node Status Register50
`TCU_NODE_STATUS51`	`0x94CC`	`32`	`RO`	`0x00000000`	TCU Node Status Register51
`TCU_NODE_STATUS52`	`0x94D0`	`32`	`RO`	`0x00000000`	TCU Node Status Register52
`TCU_NODE_STATUS53`	`0x94D4`	`32`	`RO`	`0x00000000`	TCU Node Status Register53
`TCU_NODE_STATUS54`	`0x94D8`	`32`	`RO`	`0x00000000`	TCU Node Status Register54
`TCU_NODE_STATUS55`	`0x94DC`	`32`	`RO`	`0x00000000`	TCU Node Status Register55
`TCU_NODE_STATUS56`	`0x94E0`	`32`	`RO`	`0x00000000`	TCU Node Status Register56
`TCU_NODE_STATUS57`	`0x94E4`	`32`	`RO`	`0x00000000`	TCU Node Status Register57
`TCU_NODE_STATUS58`	`0x94E8`	`32`	`RO`	`0x00000000`	TCU Node Status Register58
`TCU_NODE_STATUS59`	`0x94EC`	`32`	`RO`	`0x00000000`	TCU Node Status Register59
`TCU_NODE_STATUS60`	`0x94F0`	`32`	`RO`	`0x00000000`	TCU Node Status Register60
`TCU_NODE_STATUS61`	`0x94F4`	`32`	`RO`	`0x00000000`	TCU Node Status Register61
`SMMU_EVENTQ_PROD`	`0x100A8`	`32`	`RW`	`0x00000000`	SMMU_EVENTQ_PROD
`SMMU_EVENTQ_CONS`	`0x100AC`	`32`	`RW`	`0x00000000`	SMMU_EVENTQ_CONS
`SMMU_PRIQ_PROD`	`0x100C8`	`32`	`RW`	`0x00000000`	SMMU_PRIQ_PROD
`SMMU_PRIQ_CONS`	`0x100CC`	`32`	`RW`	`0x00000000`	SMMU_PRIQ_CONS
`SMMU_PMCG_EVCNTR0`	`0x22000`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVCNTR0
`SMMU_PMCG_EVCNTR1`	`0x22004`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVCNTR1
`SMMU_PMCG_EVCNTR2`	`0x22008`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVCNTR2
`SMMU_PMCG_EVCNTR3`	`0x2200C`	`32`	`RW`	`0x00000000`	SMMU_PMCG_EVCNTR3
`SMMU_PMCG_SVR0`	`0x22600`	`32`	`RO`	`0x00000000`	SMMU_PMCG_SVR0
`SMMU_PMCG_SVR1`	`0x22604`	`32`	`RO`	`0x00000000`	SMMU_PMCG_SVR1
`SMMU_PMCG_SVR2`	`0x22608`	`32`	`RO`	`0x00000000`	SMMU_PMCG_SVR2
`SMMU_PMCG_SVR3`	`0x2260C`	`32`	`RO`	`0x00000000`	SMMU_PMCG_SVR3
`SMMU_PMCG_OVSCLR0`	`0x22C80`	`32`	`RO`	`0x00000000`	SMMU_PMCG_OVSCLR0
`SMMU_PMCG_OVSSET0`	`0x22CC0`	`32`	`RO`	`0x00000000`	SMMU_PMCG_OVSSET0
`SMMU_PMCG_CAPR`	`0x22D88`	`32`	`RO`	`0x00000000`	SMMU_PMCG_CAPR