TCU_ERRGEN_LO

         TCU_ERRGEN_LO


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16008EC0`

Size: 32

Offset: 0x8EC0

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_4` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_4` `RO 0x0`												`TCC` `RW 0x0`	`DCC` `RW 0x0`	`TWC` `RW 0x0`	`DWC` `RW 0x0`

TCU_ERRGEN_LO Fields


Bit	Name	Description	Access	Reset
31:4	`Reserved_31_4`	Reserved_31_4	`RO`	`0x0`
3	`TCC`	When 1, entries allocated into the configuration cache are written with a tag parity error.	`RW`	`0x0`
2	`DCC`	When 1, entries allocated into the configuration cache are written with a data parity error.	`RW`	`0x0`
1	`TWC`	When 1, entries allocated into any walk cache are written with a tag parity error.	`RW`	`0x0`
0	`DWC`	When 1, entries allocated into any walk cache are written with a data parity error.	`RW`	`0x0`