SMMU_S_GBPA

         SMMU_S_GBPA


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16008044`

Size: 32

Offset: 0x8044

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Update` `RW 0x0`	`Reserved_30_21` `RO 0x0`										`ABORT` `RW 0x0`	`INSTCFG` `RW 0x0`		`PRIVCFG` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`NSCFG` `RW 0x0`		`SHCFG` `RW 0x0`		`ALLOCCFG` `RW 0x0`				`Reserved_7_5` `RO 0x0`			`MTCFG` `RW 0x0`	`MemAttr` `RW 0x0`

SMMU_S_GBPA Fields


Bit	Name	Description	Access	Reset
31	`Update`	Update	`RW`	`0x0`
30:21	`Reserved_30_21`	Reserved_30_21	`RO`	`0x0`
20	`ABORT`	ABORT	`RW`	`0x0`
19:18	`INSTCFG`	INSTCFG	`RW`	`0x0`
17:16	`PRIVCFG`	PRIVCFG	`RW`	`0x0`
15:14	`NSCFG`	NSCFG	`RW`	`0x0`
13:12	`SHCFG`	SHCFG	`RW`	`0x0`
11:8	`ALLOCCFG`	ALLOCCFG	`RW`	`0x0`
7:5	`Reserved_7_5`	Reserved_7_5	`RO`	`0x0`
4	`MTCFG`	MTCFG	`RW`	`0x0`
3:0	`MemAttr`	MemAttr	`RW`	`0x0`