TCU_CTRL 

         The TCU Control register disables TCU features.  You can disable individual walk caches, which can improve performance in some systems if the hit rate of the individual walk cache is very low.  Do not modify the other bits unless directed to by Arm.
Module Instance Base Address Register Address
i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000 0x16000000 0x16008E00

Size: 32

Offset: 0x8E00

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AUX31

RW 0x0

AUX30

RW 0x0

AUX29

RW 0x0

AUX28

RW 0x0

AUX27

RW 0x0

AUX26

RW 0x0

AUX25

RW 0x0

AUX24

RW 0x0

AUX23

RW 0x0

AUX22

RW 0x0

AUX21

RW 0x0

AUX20

RW 0x0

AUX19

RW 0x0

AUX18

RW 0x0

AUX17

RW 0x0

AUX16

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WCS2L3_DIS

RW 0x0

WCS2L2_DIS

RW 0x0

WCS2L1_DIS

RW 0x0

WCS2L0_DIS

RW 0x0

WCS1L3_DIS

RW 0x0

WCS1L2_DIS

RW 0x0

WCS1L1_DIS

RW 0x0

WCS1L0_DIS

RW 0x0

AUX7

RW 0x0

AUX6

RW 0x0

AUX5

RW 0x0

AUX4

RW 0x0

AUX3

RW 0x0

AUX2

RW 0x0

AUX1

RW 0x0

AUX0

RW 0x0

TCU_CTRL Fields

Bit Name Description Access Reset
31 AUX31 
Leave this bit as zero.
 RW 0x0
30 AUX30 
Leave this bit as zero.
 RW 0x0
29 AUX29 
Leave this bit as zero.
 RW 0x0
28 AUX28 
Leave this bit as zero.
 RW 0x0
27 AUX27 
Leave this bit as zero.
 RW 0x0
26 AUX26 
Leave this bit as zero.
 RW 0x0
25 AUX25 
Leave this bit as zero.
 RW 0x0
24 AUX24 
Leave this bit as zero.
 RW 0x0
23 AUX23 
Leave this bit as zero.
 RW 0x0
22 AUX22 
Leave this bit as zero.
 RW 0x0
21 AUX21 
Leave this bit as zero.
 RW 0x0
20 AUX20 
Leave this bit as zero.
 RW 0x0
19 AUX19 
Leave this bit as zero.
 RW 0x0
18 AUX18 
Leave this bit as zero.
 RW 0x0
17 AUX17 
Leave this bit as zero.
 RW 0x0
16 AUX16 
Leave this bit as zero.
 RW 0x0
15 WCS2L3_DIS 
Walk cache disable. When this bit is set to 1, the stage 2 level 3 walk cache is disabled.
 RW 0x0
14 WCS2L2_DIS 
Walk cache disable. When this bit is set to 1, the stage 2 level 2 walk cache is disabled.
 RW 0x0
13 WCS2L1_DIS 
Walk cache disable. When this bit is set to 1, the stage 2 level 1 walk cache is disabled.
 RW 0x0
12 WCS2L0_DIS 
Walk cache disable. When this bit is set to 1, the stage 2 level 0 walk cache is disabled.
 RW 0x0
11 WCS1L3_DIS 
Walk cache disable. When this bit is set to 1, the stage 1 level 3 walk cache is disabled.
 RW 0x0
10 WCS1L2_DIS 
Walk cache disable. When this bit is set to 1, the stage 1 level 2 walk cache is disabled.
 RW 0x0
9 WCS1L1_DIS 
Walk cache disable. When this bit is set to 1, the stage 1 level 1 walk cache is disabled.
 RW 0x0
8 WCS1L0_DIS 
Walk cache disable. When this bit is set to 1, the stage 2 level 0 walk cache is disabled.
 RW 0x0
7 AUX7 
Leave this bit as zero.
 RW 0x0
6 AUX6 
Leave this bit as zero.
 RW 0x0
5 AUX5 
Leave this bit as zero.
 RW 0x0
4 AUX4 
Leave this bit as zero.
 RW 0x0
3 AUX3 
Leave this bit as zero.
 RW 0x0
2 AUX2 
Leave this bit as zero.
 RW 0x0
1 AUX1 
Leave this bit as zero.
 RW 0x0
0 AUX0 
Leave this bit as zero.
 RW 0x0