SMMU_PMCG_CFGR

         SMMU_PMCG_CFGR


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16002E00`

Size: 32

Offset: 0x2E00

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_24` `RO 0x0`								`SID_FILTER_TYPE` `RO 0x1`	`CAPTURE` `RO 0x1`	`MSI` `RO 0x0`	`RELOC_CTRS` `RO 0x1`	`Reserved_19_14` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_19_14` `RO 0x0`		`SIZE` `RO 0x1F`						`Reserved_7_6` `RO 0x0`		`NCTR` `RO 0x3`

SMMU_PMCG_CFGR Fields


Bit	Name	Description	Access	Reset
31:24	`Reserved_31_24`	Reserved_31_24	`RO`	`0x0`
23	`SID_FILTER_TYPE`	SID_FILTER_TYPE	`RO`	`0x1`
22	`CAPTURE`	CAPTURE	`RO`	`0x1`
21	`MSI`	MSI	`RO`	`0x0`
20	`RELOC_CTRS`	RELOC_CTRS	`RO`	`0x1`
19:14	`Reserved_19_14`	Reserved_19_14	`RO`	`0x0`
13:8	`SIZE`	SIZE	`RO`	`0x1F`
7:6	`Reserved_7_6`	Reserved_7_6	`RO`	`0x0`
5:0	`NCTR`	NCTR	`RO`	`0x3`