SMMU_EVENTQ_CONS

         SMMU_EVENTQ_CONS


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x160100AC`

Size: 32

Offset: 0x100AC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`OVACKFLG` `RW 0x0`	`Reserved_30_20` `RO 0x0`											`RD` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RD` `RW 0x0`

SMMU_EVENTQ_CONS Fields


Bit	Name	Description	Access	Reset
31	`OVACKFLG`	OVACKFLG	`RW`	`0x0`
30:20	`Reserved_30_20`	Reserved_30_20	`RO`	`0x0`
19:0	`RD`	RD	`RW`	`0x0`