SMMU_PIDR2
This is the TCU Peripheral ID register 2, a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register.
| Module Instance | Base Address | Register Address |
|---|---|---|
i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000
|
0x16000000
|
0x16000FE8
|
Size: 32
Offset: 0xFE8
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
|
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
|
|
|
||||||||||||
SMMU_PIDR2 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:8 |
Reserved_31_8
|
Reserved_31_8 |
RO
|
0x0
|
| 7:4 |
REVISION
|
MMU-600 major revision. The value indicates major product revision rX. |
RO
|
0x2
|
| 3 |
JEDEC
|
IC uses a manufacturer identity code that is allocated by JEDEC, according to the JEP106 specification. |
RO
|
0x1
|
| 2:0 |
DES_1
|
JEP106 ID code[6:4] for Arm. |
RO
|
0x3
|