SMMU_PIDR1

         This is the TCU Peripheral ID register 1, a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register.


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16000FE4`

Size: 32

Offset: 0xFE4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_8` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_8` `RO 0x0`								`DES_0` `RO 0xB`				`PART_1` `RO 0x4`

SMMU_PIDR1 Fields


Bit	Name	Description	Access	Reset
31:8	`Reserved_31_8`	Reserved_31_8	`RO`	`0x0`
7:4	`DES_0`	JEP106 ID code[3:0] for Arm.	`RO`	`0xB`
3:0	`PART_1`	Part number[11:8].	`RO`	`0x4`