SMMU_IDR0

         SMMU_IDR0


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16000000`

Size: 32

Offset: 0x

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_29` `RO 0x0`			`ST_LEVEL` `RO 0x1`		`TERM_MODEL` `RO 0x0`	`STALL_MODEL` `RO 0x0`		`Reserved_23_23` `RO 0x0`	`TTENDIAN` `RO 0x0`		`VATOS` `RO 0x0`	`CD2L` `RO 0x1`	`VMID16` `RO 0x1`	`VMW` `RO 0x1`	`PRI` `RO 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ATOS` `RO 0x0`	`SEV` `RO 0x0`	`MSI` `RO 0x1`	`ASID16` `RO 0x1`	`NS1ATS` `RO 0x1`	`ATS` `RO 0x1`	`HYP` `RO 0x1`	`DORMHINT` `RO 0x0`	`HTTU` `RO 0x0`		`BTM` `RO 0x0`	`COHACC` `RO 0x0`	`TTF` `RO 0x3`		`S1P` `RO 0x1`	`S2P` `RO 0x1`

SMMU_IDR0 Fields


Bit	Name	Description	Access	Reset
31:29	`Reserved_31_29`	Reserved_31_29	`RO`	`0x0`
28:27	`ST_LEVEL`	ST_LEVEL	`RO`	`0x1`
26	`TERM_MODEL`	TERM_MODEL	`RO`	`0x0`
25:24	`STALL_MODEL`	STALL_MODEL	`RO`	`0x0`
23	`Reserved_23_23`	Reserved_23_23	`RO`	`0x0`
22:21	`TTENDIAN`	TTENDIAN	`RO`	`0x0`
20	`VATOS`	VATOS	`RO`	`0x0`
19	`CD2L`	CD2L	`RO`	`0x1`
18	`VMID16`	VMID16	`RO`	`0x1`
17	`VMW`	VMW	`RO`	`0x1`
16	`PRI`	PRI	`RO`	`0x1`
15	`ATOS`	ATOS	`RO`	`0x0`
14	`SEV`	SEV	`RO`	`0x0`
13	`MSI`	MSI	`RO`	`0x1`
12	`ASID16`	ASID16	`RO`	`0x1`
11	`NS1ATS`	NS1ATS	`RO`	`0x1`
10	`ATS`	ATS	`RO`	`0x1`
9	`HYP`	HYP	`RO`	`0x1`
8	`DORMHINT`	DORMHINT	`RO`	`0x0`
7:6	`HTTU`	HTTU	`RO`	`0x0`
5	`BTM`	BTM	`RO`	`0x0`
4	`COHACC`	COHACC	`RO`	`0x0`
3:2	`TTF`	TTF	`RO`	`0x3`
1	`S1P`	S1P	`RO`	`0x1`
0	`S2P`	S2P	`RO`	`0x1`