TCU_NODE_STATUS8

         TCU_NODE_STATUS8


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16009420`

Size: 32

Offset: 0x9420

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`

TCU_NODE_STATUS8 Fields

Bit Name Description Access Reset

31:2

Bit	Name	Description	Access	Reset
31:2	`Reserved_31_2`	Reserved_31_2	`RO`	`0x0`
1	`ATS`	ATS implemented.When this bit is set to 0, the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1, the corresponding node is a PCIe Root Complex that supports ATS, and is connected to the TCU using the DTI-ATS protocol.	`RO`	`0x0`
0	`CONNECTED`	DTI link connected.When this bit is set to 0, the DTI link for the corresponding node is not connected.When this bit is set to 1, the DTI link for the corresponding node is connected.If a DTI link is not connected, accesses to TBU registers are RAZ/WI. However, the state might change between reading this register and attempting to access the TBU.	`RO`	`0x0`

Reserved_31_2

Reserved_31_2

RO

0x0

ATS

ATS implemented.When this bit is set to 0, the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1, the corresponding node is a PCIe Root Complex that supports ATS, and is connected to the TCU using the DTI-ATS protocol.

RO

0x0

CONNECTED

DTI link connected.When this bit is set to 0, the DTI link for the corresponding node is not connected.When this bit is set to 1, the DTI link for the corresponding node is connected.If a DTI link is not connected, accesses to TBU registers are RAZ/WI. However, the state might change between reading this register and attempting to access the TBU.

RO

0x0