SMMU_IDR3

         SMMU_IDR3


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x1600000C`

Size: 32

Offset: 0xC

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_6` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_6` `RO 0x0`										`PPS` `RO 0x1`	`XNX` `RO 0x1`	`PBHA` `RO 0x1`	`HAD` `RO 0x1`	`Reserved_1_0` `RO 0x0`

SMMU_IDR3 Fields


Bit	Name	Description	Access	Reset
31:6	`Reserved_31_6`	Reserved_31_6	`RO`	`0x0`
5	`PPS`	PPS	`RO`	`0x1`
4	`XNX`	XNX	`RO`	`0x1`
3	`PBHA`	PBHA	`RO`	`0x1`
2	`HAD`	HAD	`RO`	`0x1`
1:0	`Reserved_1_0`	Reserved_1_0	`RO`	`0x0`