SMMU_GERROR

         SMMU_GERROR


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16000060`

Size: 32

Offset: 0x60

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_8` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_8` `RO 0x0`								`MSI_GERROR_ABT_ERR` `RO 0x0`	`MSI_PRIQ_ABT_ERR` `RO 0x0`	`MSI_EVENTQ_ABT_ERR` `RO 0x0`	`MSI_CMDQ_ABT_ERR` `RO 0x0`	`PRIQ_ABT_ERR` `RO 0x0`	`EVENTQ_ABT_ERR` `RO 0x0`	`Reserved_1_1` `RO 0x0`	`CMDQ_ERR` `RO 0x0`

SMMU_GERROR Fields


Bit	Name	Description	Access	Reset
31:8	`Reserved_31_8`	Reserved_31_8	`RO`	`0x0`
7	`MSI_GERROR_ABT_ERR`	MSI_GERROR_ABT_ERR	`RO`	`0x0`
6	`MSI_PRIQ_ABT_ERR`	MSI_PRIQ_ABT_ERR	`RO`	`0x0`
5	`MSI_EVENTQ_ABT_ERR`	MSI_EVENTQ_ABT_ERR	`RO`	`0x0`
4	`MSI_CMDQ_ABT_ERR`	MSI_CMDQ_ABT_ERR	`RO`	`0x0`
3	`PRIQ_ABT_ERR`	PRIQ_ABT_ERR	`RO`	`0x0`
2	`EVENTQ_ABT_ERR`	EVENTQ_ABT_ERR	`RO`	`0x0`
1	`Reserved_1_1`	Reserved_1_1	`RO`	`0x0`
0	`CMDQ_ERR`	CMDQ_ERR	`RO`	`0x0`