SMMU_IDR5

         SMMU_IDR5


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16000014`

Size: 32

Offset: 0x14

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`STALL_MAX` `RO 0x40`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_15_12` `RO 0x0`				`VAX` `RO 0x0`		`Reserved_9_7` `RO 0x0`			`GRAN64K` `RO 0x1`	`GRAN16K` `RO 0x1`	`GRAN4K` `RO 0x1`	`Reserved_3_3` `RO 0x0`	`OAS` `RO 0x0`

SMMU_IDR5 Fields


Bit	Name	Description	Access	Reset
31:16	`STALL_MAX`	STALL_MAX	`RO`	`0x40`
15:12	`Reserved_15_12`	Reserved_15_12	`RO`	`0x0`
11:10	`VAX`	VAX	`RO`	`0x0`
9:7	`Reserved_9_7`	Reserved_9_7	`RO`	`0x0`
6	`GRAN64K`	GRAN64K	`RO`	`0x1`
5	`GRAN16K`	GRAN16K	`RO`	`0x1`
4	`GRAN4K`	GRAN4K	`RO`	`0x1`
3	`Reserved_3_3`	Reserved_3_3	`RO`	`0x0`
2:0	`OAS`	OAS	`RO`	`0x0`