SMMU_CR0

         SMMU_CR0


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16000020`

Size: 32

Offset: 0x20

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_9` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_9` `RO 0x0`							`VMW` `RW 0x0`			`Reserved_5_5` `RO 0x0`	`ATSCHK` `RW 0x0`	`CMDQEN` `RW 0x0`	`EVENTQEN` `RW 0x0`	`PRIQEN` `RW 0x0`	`SMMUEN` `RW 0x0`

SMMU_CR0 Fields


Bit	Name	Description	Access	Reset
31:9	`Reserved_31_9`	Reserved_31_9	`RO`	`0x0`
8:6	`VMW`	VMW	`RW`	`0x0`
5	`Reserved_5_5`	Reserved_5_5	`RO`	`0x0`
4	`ATSCHK`	ATSCHK	`RW`	`0x0`
3	`CMDQEN`	CMDQEN	`RW`	`0x0`
2	`EVENTQEN`	EVENTQEN	`RW`	`0x0`
1	`PRIQEN`	PRIQEN	`RW`	`0x0`
0	`SMMUEN`	SMMUEN	`RW`	`0x0`