SMMU_IDR1

         SMMU_IDR1


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16000004`

Size: 32

Offset: 0x4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_31` `RO 0x0`	`TABLES_PRESET` `RO 0x0`	`QUEUES_PRESET` `RO 0x0`	`REL` `RO 0x0`	`ATTR_TYPES_OVR` `RO 0x1`	`ATTR_PERMS_OVR` `RO 0x1`	`CMDQS` `RO 0x13`					`EVENTQS` `RO 0x13`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`PRIQS` `RO 0x13`					`SSIDSIZE` `RO 0x14`					`SIDSIZE` `RO 0x18`

SMMU_IDR1 Fields


Bit	Name	Description	Access	Reset
31	`Reserved_31_31`	Reserved_31_31	`RO`	`0x0`
30	`TABLES_PRESET`	TABLES_PRESET	`RO`	`0x0`
29	`QUEUES_PRESET`	QUEUES_PRESET	`RO`	`0x0`
28	`REL`	REL	`RO`	`0x0`
27	`ATTR_TYPES_OVR`	ATTR_TYPES_OVR	`RO`	`0x1`
26	`ATTR_PERMS_OVR`	ATTR_PERMS_OVR	`RO`	`0x1`
25:21	`CMDQS`	CMDQS	`RO`	`0x13`
20:16	`EVENTQS`	EVENTQS	`RO`	`0x13`
15:11	`PRIQS`	PRIQS	`RO`	`0x13`
10:6	`SSIDSIZE`	SSIDSIZE	`RO`	`0x14`
5:0	`SIDSIZE`	SIDSIZE	`RO`	`0x18`