SMMU_CR2

         SMMU_CR2


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x1600002C`

Size: 32

Offset: 0x2C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_3` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_3` `RO 0x0`													`PTM` `RW 0x1`	`RECINVSID` `RW 0x0`	`E2H` `RW 0x0`

SMMU_CR2 Fields


Bit	Name	Description	Access	Reset
31:3	`Reserved_31_3`	Reserved_31_3	`RO`	`0x0`
2	`PTM`	PTM	`RW`	`0x1`
1	`RECINVSID`	RECINVSID	`RW`	`0x0`
0	`E2H`	E2H	`RW`	`0x0`