TCU_SCR 

         This is the TCU Secure Control register.
Module Instance Base Address Register Address
i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000 0x16000000 0x16008E18

Size: 32

Offset: 0x8E18

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_31_4

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_31_4

RO 0x0

NS_INIT

RW 0x0

Reserved_2_2

RO 0x0

NS_RAS

RW 0x0

NS_UARCH

RW 0x0

TCU_SCR Fields

Bit Name Description Access Reset
31:4 Reserved_31_4 
Reserved_31_4
 RO 0x0
3 NS_INIT 
Non-secure register access to SMMU_S_INIT. When this bit is set to 0, Non-secure accesses to the SMMU_S_INIT register are RAZ/WI.
 RW 0x0
2 Reserved_2_2 
Reserved_2_2
 RO 0x0
1 NS_RAS 
Non-secure register access permitted for RAS registers. When this bit is set to 0, Non-secure accesses to register addresses 0x08E80-0x08EBC are RAZ/WI.The sec_override input signal defines the reset value of this bit.
 RW 0x0
0 NS_UARCH 
Non-secure register access permitted for MMU-600 registers. When this bit is set to 0, Non-secure accesses to register addresses 0x08E00-0x08E7C and 0x09000-0x093FC are RAZ/WI.The sec_override input signal defines the reset value of this bit.Arm recommends setting this bit to 0 if your implementation might use Secure translation.
 RW 0x0