TCU_ERRSTATUS_LO 

         TCU_ERRSTATUS_LO
Module Instance Base Address Register Address
i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000 0x16000000 0x16008E90

Size: 32

Offset: 0x8E90

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_31_31

RO 0x0

V

RW 0x0

Reserved_29_28

RO 0x0

OF

RW 0x0

Reserved_26_26

RO 0x0

CE

RW 0x0

Reserved_23_16

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IERR

RW 0x0

SERR

RW 0x0

TCU_ERRSTATUS_LO Fields

Bit Name Description Access Reset
31 Reserved_31_31 
Reserved_31_31
 RO 0x0
30 V 
Register valid. This bit is set to 1 to indicate that at least one RAS error was recorded. Clear this bit by writing a 1 to it. If CE is not 00 and is not being cleared, the write is ignored. A write of 0 is ignored.
 RW 0x0
29:28 Reserved_29_28 
Reserved_29_28
 RO 0x0
27 OF 
Overflow. This bit is set to 1 to indicate that multiple errors were recorded. Clear this bit by writing a 1 to it. A write of 0 is ignored.
 RW 0x0
26 Reserved_26_26 
Reserved_26_26
 RO 0x0
25:24 CE 
Correctable Error. This field is set to 1 to indicate that a corrected error occurred. Clear this bit by writing a 11 to it. If OF is set to 1 and is not being cleared, the write is ignored. A write of any value other than 11 is ignored.
 RW 0x0
23:16 Reserved_23_16 
Reserved_23_16
 RO 0x0
15:8 IERR 
Implementation defined error code.  When SERR is not set to 0, this field indicates the source of the error, as follows:   0x00 Stage 1, level 0 walk cache.   0x01 Stage 1, level 1 walk cache.   0x02 Stage 1, level 2 walk cache.   0x03 Stage 1, level 3 walk cache.   0x04 Stage 2, level 0 walk cache.   0x05 Stage 2, level 1 walk cache.   0x06 Stage 2, level 2 walk cache.   0x07 Stage 2, level 3 walk cache.   Writes to this field are ignored.
 RW 0x0
7:0 SERR 
Error code. This read-only field provides information about the earliest unacknowledged correctable error, as follows:   0x00 No error. This occurs when CE = 00.   0x07 Tag corrupted. This can occur when CE != 00.   0x08 Data corrupted. This can occur when CE != 00.
RW 0x0