SMMU_CR1

         SMMU_CR1


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16000028`

Size: 32

Offset: 0x28

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_12` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_12` `RO 0x0`				`TABLE_SH` `RW 0x0`		`TABLE_OC` `RW 0x0`		`TABLE_IC` `RW 0x0`		`QUEUE_SH` `RW 0x0`		`QUEUE_OC` `RW 0x0`		`QUEUE_IC` `RW 0x0`

SMMU_CR1 Fields


Bit	Name	Description	Access	Reset
31:12	`Reserved_31_12`	Reserved_31_12	`RO`	`0x0`
11:10	`TABLE_SH`	TABLE_SH	`RW`	`0x0`
9:8	`TABLE_OC`	TABLE_OC	`RW`	`0x0`
7:6	`TABLE_IC`	TABLE_IC	`RW`	`0x0`
5:4	`QUEUE_SH`	QUEUE_SH	`RW`	`0x0`
3:2	`QUEUE_OC`	QUEUE_OC	`RW`	`0x0`
1:0	`QUEUE_IC`	QUEUE_IC	`RW`	`0x0`