SMMU_PMCG_SCR

         SMMU_PMCG_SCR


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16002DF8`

Size: 32

Offset: 0x2DF8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`READS_AS_ONE` `RW 0x1`	`Reserved_30_3` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_30_3` `RO 0x0`													`NSMSI` `RW 0x0`	`NSRA` `RW 0x1`	`SO` `RW 0x0`

SMMU_PMCG_SCR Fields


Bit	Name	Description	Access	Reset
31	`READS_AS_ONE`	READS_AS_ONE	`RW`	`0x1`
30:3	`Reserved_30_3`	Reserved_30_3	`RO`	`0x0`
2	`NSMSI`	NSMSI	`RW`	`0x0`
1	`NSRA`	NSRA	`RW`	`0x1`
0	`SO`	SO	`RW`	`0x0`