SMMU_PMCG_PIDR5
This is the PMU Peripheral ID register 5. This is a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register.
| Module Instance | Base Address | Register Address |
|---|---|---|
i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000
|
0x16000000
|
0x16002FD4
|
Size: 32
Offset: 0x2FD4
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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SMMU_PMCG_PIDR5 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:8 |
Reserved_31_8
|
Reserved_31_8 |
RO
|
0x0
|
| 7:0 |
Reserved
|
Reserved. |
RO
|
0x0
|