SMMU_PMCG_PMAUTHSTATUS

         SMMU_PMCG_PMAUTHSTATUS


Module Instance	Base Address	Register Address
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`	`0x16000000`	`0x16002FB8`

Size: 32

Offset: 0x2FB8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_31_8` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_31_8` `RO 0x0`								`SNI` `RO 0x0`	`SNE` `RO 0x0`	`SI` `RO 0x0`	`SE` `RO 0x0`	`NSNI` `RO 0x0`	`NSNE` `RO 0x0`	`NSI` `RO 0x0`	`NSE` `RO 0x0`

SMMU_PMCG_PMAUTHSTATUS Fields


Bit	Name	Description	Access	Reset
31:8	`Reserved_31_8`	Reserved_31_8	`RO`	`0x0`
7	`SNI`	SNI	`RO`	`0x0`
6	`SNE`	SNE	`RO`	`0x0`
5	`SI`	SI	`RO`	`0x0`
4	`SE`	SE	`RO`	`0x0`
3	`NSNI`	NSNI	`RO`	`0x0`
2	`NSNE`	NSNE	`RO`	`0x0`
1	`NSI`	NSI	`RO`	`0x0`
0	`NSE`	NSE	`RO`	`0x0`