smmu_tcu Summary

TCU Registers

Base Address: 0x16000000


Register Address Offset	Bit Fields
`i_aps_smmu__sys_tcu_apb__16000000__tcu__SEG_TCU_s_0x0_0x1000000`
`SMMU_IDR0` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_29` `RO 0x0`			`ST_LEVEL` `RO 0x1`		`TERM_MODEL` `RO 0x0`	`STALL_MODEL` `RO 0x0`		`Reserved_23_23` `RO 0x0`	`TTENDIAN` `RO 0x0`		`VATOS` `RO 0x0`	`CD2L` `RO 0x1`	`VMID16` `RO 0x1`	`VMW` `RO 0x1`	`PRI` `RO 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ATOS` `RO 0x0`	`SEV` `RO 0x0`	`MSI` `RO 0x1`	`ASID16` `RO 0x1`	`NS1ATS` `RO 0x1`	`ATS` `RO 0x1`	`HYP` `RO 0x1`	`DORMHINT` `RO 0x0`	`HTTU` `RO 0x0`		`BTM` `RO 0x0`	`COHACC` `RO 0x0`	`TTF` `RO 0x3`		`S1P` `RO 0x1`	`S2P` `RO 0x1`
`SMMU_IDR1` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`TABLES_PRESET` `RO 0x0`	`QUEUES_PRESET` `RO 0x0`	`REL` `RO 0x0`	`ATTR_TYPES_OVR` `RO 0x1`	`ATTR_PERMS_OVR` `RO 0x1`	`CMDQS` `RO 0x13`					`EVENTQS` `RO 0x13`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PRIQS` `RO 0x13`					`SSIDSIZE` `RO 0x14`					`SIDSIZE` `RO 0x18`
`SMMU_IDR2` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_10` `RO 0x0`						`BA_VATOS` `RO 0x0`
`SMMU_IDR3` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_6` `RO 0x0`										`PPS` `RO 0x1`	`XNX` `RO 0x1`	`PBHA` `RO 0x1`	`HAD` `RO 0x1`	`Reserved_1_0` `RO 0x0`
`SMMU_IDR5` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`STALL_MAX` `RO 0x40`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_12` `RO 0x0`				`VAX` `RO 0x0`		`Reserved_9_7` `RO 0x0`			`GRAN64K` `RO 0x1`	`GRAN16K` `RO 0x1`	`GRAN4K` `RO 0x1`	`Reserved_3_3` `RO 0x0`	`OAS` `RO 0x0`
`SMMU_IIDR` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ProductID` `RO 0x483`												`Variant` `RO 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Revision` `RO 0x0`				`Implementer` `RO 0x43B`
`SMMU_AIDR` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`ArchMajorRev` `RO 0x0`				`ArchMinorRev` `RO 0x1`
`SMMU_CR0` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_9` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_9` `RO 0x0`							`VMW` `RW 0x0`			`Reserved_5_5` `RO 0x0`	`ATSCHK` `RW 0x0`	`CMDQEN` `RW 0x0`	`EVENTQEN` `RW 0x0`	`PRIQEN` `RW 0x0`	`SMMUEN` `RW 0x0`
`SMMU_CR0ACK` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_9` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_9` `RO 0x0`							`VMW` `RO 0x0`			`Reserved_5_5` `RO 0x0`	`ATSCHK` `RO 0x0`	`CMDQEN` `RO 0x0`	`EVENTQEN` `RO 0x0`	`PRIQEN` `RO 0x0`	`SMMUEN` `RO 0x0`
`SMMU_CR1` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_12` `RO 0x0`				`TABLE_SH` `RW 0x0`		`TABLE_OC` `RW 0x0`		`TABLE_IC` `RW 0x0`		`QUEUE_SH` `RW 0x0`		`QUEUE_OC` `RW 0x0`		`QUEUE_IC` `RW 0x0`
`SMMU_CR2` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`PTM` `RW 0x1`	`RECINVSID` `RW 0x0`	`E2H` `RW 0x0`
`SMMU_GBPA` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Update` `RW 0x0`	`Reserved_30_21` `RO 0x0`										`ABORT` `RW 0x0`	`INSTCFG` `RW 0x0`		`PRIVCFG` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`SHCFG` `RW 0x0`		`ALLOCCFG` `RW 0x0`				`Reserved_7_5` `RO 0x0`			`MTCFG` `RW 0x0`	`MemAttr` `RW 0x0`
`SMMU_IRQ_CTRL` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`EVENTQ_IRQEN` `RW 0x0`	`PRIQ_IRQEN` `RW 0x0`	`GERROR_IRQEN` `RW 0x0`
`SMMU_IRQ_CTRLACK` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`EVENTQ_IRQEN` `RO 0x0`	`PRIQ_IRQEN` `RO 0x0`	`GERROR_IRQEN` `RO 0x0`
`SMMU_GERROR` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`MSI_GERROR_ABT_ERR` `RO 0x0`	`MSI_PRIQ_ABT_ERR` `RO 0x0`	`MSI_EVENTQ_ABT_ERR` `RO 0x0`	`MSI_CMDQ_ABT_ERR` `RO 0x0`	`PRIQ_ABT_ERR` `RO 0x0`	`EVENTQ_ABT_ERR` `RO 0x0`	`Reserved_1_1` `RO 0x0`	`CMDQ_ERR` `RO 0x0`
`SMMU_GERRORN` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`MSI_GERROR_ABT_ERR` `RW 0x0`	`MSI_PRIQ_ABT_ERR` `RW 0x0`	`MSI_EVENTQ_ABT_ERR` `RW 0x0`	`MSI_CMDQ_ABT_ERR` `RW 0x0`	`PRIQ_ABT_ERR` `RW 0x0`	`EVENTQ_ABT_ERR` `RW 0x0`	`Reserved_1_1` `RO 0x0`	`CMDQ_ERR` `RW 0x0`
`SMMU_GERROR_IRQ_CFG0_LO` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`														`Reserved_1_0` `RO 0x0`
`SMMU_GERROR_IRQ_CFG0_HI` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_GERROR_IRQ_CFG1` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DATA` `RW 0x0`
`SMMU_GERROR_IRQ_CFG2` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_6` `RO 0x0`										`SH` `RW 0x0`		`MemAttr` `RW 0x0`
`SMMU_STRTAB_BASE_LO` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`										`Reserved_5_0` `RO 0x0`
`SMMU_STRTAB_BASE_HI` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`RA` `RW 0x0`	`Reserved_29_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_STRTAB_BASE_CFG` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_18` `RO 0x0`														`FMT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_11` `RO 0x0`					`SPLIT` `RW 0x0`					`LOG2SIZE` `RW 0x0`
`SMMU_CMDQ_BASE_LO` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`											`LOG2SIZE` `RW 0x0`
`SMMU_CMDQ_BASE_HI` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`RA` `RW 0x0`	`Reserved_29_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_CMDQ_PROD` `0x152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_20` `RO 0x0`												`WR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WR` `RW 0x0`
`SMMU_CMDQ_CONS` `0x156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`ERR` `RW 0x0`							`Reserved_23_20` `RO 0x0`				`RD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RD` `RW 0x0`
`SMMU_EVENTQ_BASE_LO` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`											`LOG2SIZE` `RW 0x0`
`SMMU_EVENTQ_BASE_HI` `0x164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`WA` `RW 0x0`	`Reserved_29_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_EVENTQ_IRQ_CFG0_LO` `0x176` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`														`Reserved_1_0` `RO 0x0`
`SMMU_EVENTQ_IRQ_CFG0_HI` `0x180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_EVENTQ_IRQ_CFG1` `0x184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DATA` `RW 0x0`
`SMMU_EVENTQ_IRQ_CFG2` `0x188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_6` `RO 0x0`										`SH` `RW 0x0`		`MemAttr` `RW 0x0`
`SMMU_PRIQ_BASE_LO` `0x192` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`											`LOG2SIZE` `RW 0x0`
`SMMU_PRIQ_BASE_HI` `0x196` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`WA` `RW 0x0`	`Reserved_29_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_PRIQ_IRQ_CFG0_LO` `0x208` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`														`Reserved_1_0` `RO 0x0`
`SMMU_PRIQ_IRQ_CFG0_HI` `0x212` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_PRIQ_IRQ_CFG1` `0x216` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DATA` `RW 0x0`
`SMMU_PRIQ_IRQ_CFG2` `0x220` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LO` `RW 0x0`	`Reserved_30_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_30_6` `RO 0x0`										`SH` `RW 0x0`		`MemAttr` `RW 0x0`
`SMMU_PIDR4` `0x4048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`SIZE` `RO 0x0`				`DES_2` `RO 0x4`
`SMMU_PIDR5` `0x4052` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`Reserved`
`SMMU_PIDR6` `0x4056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`Reserved`
`SMMU_PIDR7` `0x4060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`Reserved`
`SMMU_PIDR0` `0x4064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PART_0` `RO 0x83`
`SMMU_PIDR1` `0x4068` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`DES_0` `RO 0xB`				`PART_1` `RO 0x4`
`SMMU_PIDR2` `0x4072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`REVISION` `RO 0x2`				`JEDEC` `RO 0x1`	`DES_1` `RO 0x3`
`SMMU_PIDR3` `0x4076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`REVAND` `RO 0x2`				`CMOD` `RO 0x0`
`SMMU_CIDR0` `0x4080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PREAMBLE` `RO 0xD`
`SMMU_CIDR1` `0x4084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`CLASS` `RO 0xF`				`PREAMBLE` `RO 0x0`
`SMMU_CIDR2` `0x4088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PREAMBLE` `RO 0x5`
`SMMU_CIDR3` `0x4092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PREAMBLE` `RO 0xB1`
`SMMU_PMCG_EVTYPER0` `0x9216` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVFCAP` `RW 0x0`	`FILTER_SEC_SID` `RW 0x0`	`FILTER_SID_SPAN` `RW 0x0`	`Reserved_28_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_28_8` `RO 0x0`								`EVNT` `RW 0x0`
`SMMU_PMCG_EVTYPER1` `0x9220` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVFCAP` `RW 0x0`	`Reserved_30_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_30_8` `RO 0x0`								`EVNT` `RW 0x0`
`SMMU_PMCG_EVTYPER2` `0x9224` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVFCAP` `RW 0x0`	`Reserved_30_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_30_8` `RO 0x0`								`EVNT` `RW 0x0`
`SMMU_PMCG_EVTYPER3` `0x9228` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVFCAP` `RW 0x0`	`Reserved_30_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_30_8` `RO 0x0`								`EVNT` `RW 0x0`
`SMMU_PMCG_SMR0` `0x10752` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_24` `RO 0x0`								`STREAMID` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`STREAMID` `RW 0x0`
`SMMU_PMCG_CNTENSET0` `0x11264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`CNTEN` `RW 0x0`
`SMMU_PMCG_CNTENCLR0` `0x11296` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`CNTEN` `RW 0x0`
`SMMU_PMCG_INTENSET0` `0x11328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`INTEN` `RW 0x0`
`SMMU_PMCG_INTENCLR0` `0x11360` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`INTEN` `RW 0x0`
`SMMU_PMCG_SCR` `0x11768` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`READS_AS_ONE` `RW 0x1`	`Reserved_30_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_30_3` `RO 0x0`													`NSMSI` `RW 0x0`	`NSRA` `RW 0x1`	`SO` `RW 0x0`
`SMMU_PMCG_CFGR` `0x11776` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_24` `RO 0x0`								`SID_FILTER_TYPE` `RO 0x1`	`CAPTURE` `RO 0x1`	`MSI` `RO 0x0`	`RELOC_CTRS` `RO 0x1`	`Reserved_19_14` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_19_14` `RO 0x0`		`SIZE` `RO 0x1F`						`Reserved_7_6` `RO 0x0`		`NCTR` `RO 0x3`
`SMMU_PMCG_CR` `0x11780` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_1` `RO 0x0`															`E` `RW 0x0`
`SMMU_PMCG_CEID0_LO` `0x11808` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`N` `RO 0x7F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`N` `RO 0x7F`
`SMMU_PMCG_CEID0_HI` `0x11812` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`N` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`N` `RO 0x0`
`SMMU_PMCG_CEID1_LO` `0x11816` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`N` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`N` `RO 0x0`
`SMMU_PMCG_CEID1_HI` `0x11820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`N` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`N` `RO 0x0`
`SMMU_PMCG_IRQ_CTRL` `0x11856` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_1` `RO 0x0`															`IRQEN` `RW 0x0`
`SMMU_PMCG_IRQ_CTRLACK` `0x11860` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_1` `RO 0x0`															`IRQEN` `RO 0x0`
`SMMU_PMCG_AIDR` `0x11888` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`ARCHMAJORREV` `RO 0x0`				`ARCHMINORREV` `RO 0x1`
`SMMU_PMCG_PMAUTHSTATUS` `0x12216` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`SNI` `RO 0x0`	`SNE` `RO 0x0`	`SI` `RO 0x0`	`SE` `RO 0x0`	`NSNI` `RO 0x0`	`NSNE` `RO 0x0`	`NSI` `RO 0x0`	`NSE` `RO 0x0`
`SMMU_PMCG_PMDEVARCH` `0x12220` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ARCHITECT` `RO 0x23B`											`PRESENT` `RO 0x1`	`REVISION` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ARCHID` `RO 0x2A56`
`SMMU_PMCG_PMDEVTYPE` `0x12236` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`SUB_TYPE` `RO 0x5`				`CLS` `RO 0x6`
`SMMU_PMCG_PIDR4` `0x12240` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`SIZE` `RO 0x0`				`DES_2` `RO 0x4`
`SMMU_PMCG_PIDR5` `0x12244` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`Reserved`
`SMMU_PMCG_PIDR6` `0x12248` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`Reserved`
`SMMU_PMCG_PIDR7` `0x12252` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`Reserved`
`SMMU_PMCG_PIDR0` `0x12256` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PART_0` `RO 0x83`
`SMMU_PMCG_PIDR1` `0x12260` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`DES_0` `RO 0xB`				`PART_1` `RO 0x4`
`SMMU_PMCG_PIDR2` `0x12264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`REVISION` `RO 0x2`				`JEDEC` `RO 0x1`	`DES_1` `RO 0x3`
`SMMU_PMCG_PIDR3` `0x12268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`REVAND` `RO 0x0`				`CMOD` `RO 0x0`
`SMMU_PMCG_CIDR0` `0x12272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PREAMBLE` `RO 0xD`
`SMMU_PMCG_CIDR1` `0x12276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`CLASS` `RO 0x9`				`PREAMBLE` `RO 0x0`
`SMMU_PMCG_CIDR2` `0x12280` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PREAMBLE` `RO 0x5`
`SMMU_PMCG_CIDR3` `0x12284` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`PREAMBLE` `RO 0xB1`
`SMMU_S_IDR0` `0x32768` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_26` `RO 0x0`						`STALL_MODEL` `RO 0x0`		`Reserved_23_14` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_23_14` `RO 0x0`		`MSI` `RO 0x1`	`Reserved_12_0` `RO 0x0`
`SMMU_S_IDR1` `0x32772` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SECURE_IMPL` `RO 0x1`	`Reserved_30_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_30_6` `RO 0x0`										`S_SIDSIZE` `RO 0x18`
`SMMU_S_IDR3` `0x32780` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_7` `RO 0x0`									`SAMS` `RO 0x1`	`Reserved_5_0` `RO 0x0`
`SMMU_S_CR0` `0x32800` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_10` `RO 0x0`						`NSSTALLD` `RW 0x0`	`Reserved_8_6` `RO 0x0`			`SIF` `RW 0x0`	`Reserved_4_4` `RO 0x0`	`CMDQEN` `RW 0x0`	`EVENTQEN` `RW 0x0`	`Reserved_1_1` `RO 0x0`	`SMMUEN` `RW 0x0`
`SMMU_S_CR0ACK` `0x32804` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_10` `RO 0x0`						`NSSTALLD` `RW 0x0`	`Reserved_8_6` `RO 0x0`			`SIF` `RW 0x0`	`Reserved_4_4` `RO 0x0`	`CMDQEN` `RW 0x0`	`EVENTQEN` `RW 0x0`	`Reserved_1_1` `RO 0x0`	`SMMUEN` `RW 0x0`
`SMMU_S_CR1` `0x32808` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_12` `RO 0x0`				`TABLE_SH` `RW 0x0`		`TABLE_OC` `RW 0x0`		`TABLE_IC` `RW 0x0`		`QUEUE_SH` `RW 0x0`		`QUEUE_OC` `RW 0x0`		`QUEUE_IC` `RW 0x0`
`SMMU_S_CR2` `0x32812` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`PTM` `RW 0x0`	`RECINVSID` `RW 0x0`	`Reserved_0_0` `RO 0x0`
`SMMU_S_INIT` `0x32828` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_1` `RO 0x0`															`INV_ALL` `RW 0x0`
`SMMU_S_GBPA` `0x32836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Update` `RW 0x0`	`Reserved_30_21` `RO 0x0`										`ABORT` `RW 0x0`	`INSTCFG` `RW 0x0`		`PRIVCFG` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NSCFG` `RW 0x0`		`SHCFG` `RW 0x0`		`ALLOCCFG` `RW 0x0`				`Reserved_7_5` `RO 0x0`			`MTCFG` `RW 0x0`	`MemAttr` `RW 0x0`
`SMMU_S_IRQ_CTRL` `0x32848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`EVENTQ_IRQEN` `RW 0x0`	`Reserved_1_1` `RO 0x0`	`GERROR_IRQEN` `RW 0x0`
`SMMU_S_IRQ_CTRLACK` `0x32852` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`EVENTQ_IRQEN` `RO 0x0`	`Reserved_1_1` `RO 0x0`	`GERROR_IRQEN` `RO 0x0`
`SMMU_S_GERROR` `0x32864` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`MSI_GERROR_ABT_ERR` `RO 0x0`	`Reserved_6_6` `RO 0x0`	`MSI_EVENTQ_ABT_ERR` `RO 0x0`	`MSI_CMDQ_ABT_ERR` `RO 0x0`	`Reserved_3_3` `RO 0x0`	`EVENTQ_ABT_ERR` `RO 0x0`	`Reserved_1_1` `RO 0x0`	`CMDQ_ERR` `RO 0x0`
`SMMU_S_GERRORN` `0x32868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`MSI_GERROR_ABT_ERR` `RW 0x0`	`Reserved_6_6` `RO 0x0`	`MSI_EVENTQ_ABT_ERR` `RW 0x0`	`MSI_CMDQ_ABT_ERR` `RW 0x0`	`Reserved_3_3` `RO 0x0`	`EVENTQ_ABT_ERR` `RW 0x0`	`Reserved_1_1` `RO 0x0`	`CMDQ_ERR` `RW 0x0`
`SMMU_S_GERROR_IRQ_CFG0_LO` `0x32872` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`														`Reserved_1_0` `RO 0x0`
`SMMU_S_GERROR_IRQ_CFG0_HI` `0x32876` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_S_GERROR_IRQ_CFG1` `0x32880` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DATA` `RW 0x0`
`SMMU_S_GERROR_IRQ_CFG2` `0x32884` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_6` `RO 0x0`										`SH` `RW 0x0`		`MemAttr` `RW 0x0`
`SMMU_S_STRTAB_BASE_LO` `0x32896` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`										`Reserved_5_0` `RO 0x0`
`SMMU_S_STRTAB_BASE_HI` `0x32900` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`RA` `RW 0x0`	`Reserved_29_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_S_STRTAB_BASE_CFG` `0x32904` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_18` `RO 0x0`														`FMT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_11` `RO 0x0`					`SPLIT` `RW 0x0`					`LOG2SIZE` `RW 0x0`
`SMMU_S_CMDQ_BASE_LO` `0x32912` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`											`LOG2SIZE` `RW 0x0`
`SMMU_S_CMDQ_BASE_HI` `0x32916` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`RA` `RW 0x0`	`Reserved_29_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_S_CMDQ_PROD` `0x32920` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_20` `RO 0x0`												`WR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WR` `RW 0x0`
`SMMU_S_CMDQ_CONS` `0x32924` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`ERR` `RW 0x0`							`Reserved_23_20` `RO 0x0`				`RD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RD` `RW 0x0`
`SMMU_S_EVENTQ_BASE_LO` `0x32928` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`											`LOG2SIZE` `RW 0x0`
`SMMU_S_EVENTQ_BASE_HI` `0x32932` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`WA` `RW 0x0`	`Reserved_29_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_S_EVENTQ_PROD` `0x32936` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVFLG` `RW 0x0`	`Reserved_30_20` `RO 0x0`											`WR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WR` `RW 0x0`
`SMMU_S_EVENTQ_CONS` `0x32940` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVACKFLG` `RW 0x0`	`Reserved_30_20` `RO 0x0`											`RD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RD` `RW 0x0`
`SMMU_S_EVENTQ_IRQ_CFG0_LO` `0x32944` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`														`Reserved_1_0` `RO 0x0`
`SMMU_S_EVENTQ_IRQ_CFG0_HI` `0x32948` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR` `RW 0x0`
`SMMU_S_EVENTQ_IRQ_CFG1` `0x32952` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DATA` `RW 0x0`
`SMMU_S_EVENTQ_IRQ_CFG2` `0x32956` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_6` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_6` `RO 0x0`										`SH` `RW 0x0`		`MemAttr` `RW 0x0`
`TCU_CTRL` `0x36352` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AUX31` `RW 0x0`	`AUX30` `RW 0x0`	`AUX29` `RW 0x0`	`AUX28` `RW 0x0`	`AUX27` `RW 0x0`	`AUX26` `RW 0x0`	`AUX25` `RW 0x0`	`AUX24` `RW 0x0`	`AUX23` `RW 0x0`	`AUX22` `RW 0x0`	`AUX21` `RW 0x0`	`AUX20` `RW 0x0`	`AUX19` `RW 0x0`	`AUX18` `RW 0x0`	`AUX17` `RW 0x0`	`AUX16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WCS2L3_DIS` `RW 0x0`	`WCS2L2_DIS` `RW 0x0`	`WCS2L1_DIS` `RW 0x0`	`WCS2L0_DIS` `RW 0x0`	`WCS1L3_DIS` `RW 0x0`	`WCS1L2_DIS` `RW 0x0`	`WCS1L1_DIS` `RW 0x0`	`WCS1L0_DIS` `RW 0x0`	`AUX7` `RW 0x0`	`AUX6` `RW 0x0`	`AUX5` `RW 0x0`	`AUX4` `RW 0x0`	`AUX3` `RW 0x0`	`AUX2` `RW 0x0`	`AUX1` `RW 0x0`	`AUX0` `RW 0x0`
`TCU_QOS` `0x36356` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_28` `RO 0x0`				`QOS_DVMSYNC` `RW 0x0`				`QOS_MSI` `RW 0x0`				`QOS_QUEUE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`QOS_PTW3` `RW 0x0`				`QOS_PTW2` `RW 0x0`				`QOS_PTW1` `RW 0x0`				`QOS_PTW0` `RW 0x0`
`TCU_CFG` `0x36360` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`XLATE_SLOTS` `RO 0x40`												`Reserved_3_0` `RO 0x0`
`TCU_STATUS` `0x36368` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`GNT_XLATE_SLOTS` `RO 0x0`												`Reserved_3_0` `RO 0x0`
`TCU_SCR` `0x36376` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`NS_INIT` `RW 0x0`	`Reserved_2_2` `RO 0x0`	`NS_RAS` `RW 0x0`	`NS_UARCH` `RW 0x0`
`TCU_ERRFR_LO` `0x36480` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`FI` `RO 0x2`		`Reserved_5_2` `RO 0x0`				`ED` `RO 0x1`
`TCU_ERRFR_HI` `0x36484` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_0` `RO 0x0`
`TCU_ERRCTLR_LO` `0x36488` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`FI` `RW 0x1`	`Reserved_2_0` `RO 0x0`
`TCU_ERRCTLR_HI` `0x36492` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_0` `RO 0x0`
`TCU_ERRSTATUS_LO` `0x36496` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_31` `RO 0x0`	`V` `RW 0x0`	`Reserved_29_28` `RO 0x0`		`OF` `RW 0x0`	`Reserved_26_26` `RO 0x0`	`CE` `RW 0x0`		`Reserved_23_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`IERR` `RW 0x0`								`SERR` `RW 0x0`
`TCU_ERRSTATUS_HI` `0x36500` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_0` `RO 0x0`
`TCU_ERRGEN_LO` `0x36544` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`TCC` `RW 0x0`	`DCC` `RW 0x0`	`TWC` `RW 0x0`	`DWC` `RW 0x0`
`TCU_ERRGEN_HI` `0x36548` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_0` `RO 0x0`
`TCU_NODE_CTRL0` `0x36864` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL1` `0x36868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL2` `0x36872` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL3` `0x36876` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL4` `0x36880` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL5` `0x36884` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL6` `0x36888` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL7` `0x36892` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL8` `0x36896` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL9` `0x36900` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL10` `0x36904` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL11` `0x36908` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL12` `0x36912` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL13` `0x36916` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL14` `0x36920` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL15` `0x36924` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL16` `0x36928` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL17` `0x36932` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL18` `0x36936` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL19` `0x36940` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL20` `0x36944` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL21` `0x36948` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL22` `0x36952` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL23` `0x36956` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL24` `0x36960` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL25` `0x36964` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL26` `0x36968` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL27` `0x36972` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL28` `0x36976` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL29` `0x36980` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL30` `0x36984` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL31` `0x36988` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL32` `0x36992` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL33` `0x36996` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL34` `0x37000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL35` `0x37004` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL36` `0x37008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL37` `0x37012` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL38` `0x37016` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL39` `0x37020` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL40` `0x37024` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL41` `0x37028` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL42` `0x37032` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL43` `0x37036` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL44` `0x37040` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL45` `0x37044` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL46` `0x37048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL47` `0x37052` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL48` `0x37056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL49` `0x37060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL50` `0x37064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL51` `0x37068` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL52` `0x37072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL53` `0x37076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL54` `0x37080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL55` `0x37084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL56` `0x37088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL57` `0x37092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL58` `0x37096` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL59` `0x37100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL60` `0x37104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_CTRL61` `0x37108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_5` `RO 0x0`											`DIS_DVM` `RW 0x0`	`Reserved_3_2` `RO 0x0`		`PRI_LEVEL` `RW 0x0`
`TCU_NODE_STATUS0` `0x37888` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS1` `0x37892` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS2` `0x37896` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS3` `0x37900` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS4` `0x37904` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS5` `0x37908` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS6` `0x37912` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS7` `0x37916` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS8` `0x37920` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS9` `0x37924` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS10` `0x37928` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS11` `0x37932` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS12` `0x37936` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS13` `0x37940` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS14` `0x37944` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS15` `0x37948` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS16` `0x37952` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS17` `0x37956` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS18` `0x37960` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS19` `0x37964` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS20` `0x37968` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS21` `0x37972` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS22` `0x37976` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS23` `0x37980` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS24` `0x37984` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS25` `0x37988` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS26` `0x37992` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS27` `0x37996` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS28` `0x38000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS29` `0x38004` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS30` `0x38008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS31` `0x38012` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS32` `0x38016` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS33` `0x38020` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS34` `0x38024` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS35` `0x38028` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS36` `0x38032` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS37` `0x38036` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS38` `0x38040` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS39` `0x38044` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS40` `0x38048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS41` `0x38052` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS42` `0x38056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS43` `0x38060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS44` `0x38064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS45` `0x38068` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS46` `0x38072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS47` `0x38076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS48` `0x38080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS49` `0x38084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS50` `0x38088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS51` `0x38092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS52` `0x38096` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS53` `0x38100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS54` `0x38104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS55` `0x38108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS56` `0x38112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS57` `0x38116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS58` `0x38120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS59` `0x38124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS60` `0x38128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`TCU_NODE_STATUS61` `0x38132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`ATS` `RO 0x0`	`CONNECTED` `RO 0x0`
`SMMU_EVENTQ_PROD` `0x65704` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVFLG` `RW 0x0`	`Reserved_30_20` `RO 0x0`											`WR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WR` `RW 0x0`
`SMMU_EVENTQ_CONS` `0x65708` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVACKFLG` `RW 0x0`	`Reserved_30_20` `RO 0x0`											`RD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RD` `RW 0x0`
`SMMU_PRIQ_PROD` `0x65736` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVFLG` `RW 0x0`	`Reserved_30_20` `RO 0x0`											`WR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WR` `RW 0x0`
`SMMU_PRIQ_CONS` `0x65740` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OVACKFLG` `RW 0x0`	`Reserved_30_20` `RO 0x0`											`RD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RD` `RW 0x0`
`SMMU_PMCG_EVCNTR0` `0x139264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`COUNTER_VALUE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`COUNTER_VALUE` `RW 0x0`
`SMMU_PMCG_EVCNTR1` `0x139268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`COUNTER_VALUE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`COUNTER_VALUE` `RW 0x0`
`SMMU_PMCG_EVCNTR2` `0x139272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`COUNTER_VALUE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`COUNTER_VALUE` `RW 0x0`
`SMMU_PMCG_EVCNTR3` `0x139276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`COUNTER_VALUE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`COUNTER_VALUE` `RW 0x0`
`SMMU_PMCG_SVR0` `0x140800` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SHADOW_COUNTER_VALUE` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SHADOW_COUNTER_VALUE` `RO 0x0`
`SMMU_PMCG_SVR1` `0x140804` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SHADOW_COUNTER_VALUE` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SHADOW_COUNTER_VALUE` `RO 0x0`
`SMMU_PMCG_SVR2` `0x140808` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SHADOW_COUNTER_VALUE` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SHADOW_COUNTER_VALUE` `RO 0x0`
`SMMU_PMCG_SVR3` `0x140812` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SHADOW_COUNTER_VALUE` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SHADOW_COUNTER_VALUE` `RO 0x0`
`SMMU_PMCG_OVSCLR0` `0x142464` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`OVS` `RW 0x0`
`SMMU_PMCG_OVSSET0` `0x142528` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`OVS` `RW 0x0`
`SMMU_PMCG_CAPR` `0x142728` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_1` `RO 0x0`															`CAPTURE` `WO 0x0`