DWC_usb31_block_gbl Address Map

Global SoC Bus Configuration Register 0
  
  This register configures system bus DMA options for the master bus, which may be configured as AHB, AXI, or Native. Options include burst length and cache type (bufferable/posted, cacheable/snoop, and so on). The application can program this register upon power-on, or a change in mode of operation after the DMA engine is halted.
  
  xHCI Register Power-On Value:
  
  If you are using a standard xHCI host driver, make sure to set the register's power-on value during coreConsultant configuration (DWC_USB31_GSBUSCFG0_INIT parameter) because the standard xHCI driver does not access this register.
  
  For more details on this register, refer to the following sections:
   - <link:ext>07_Registers_additional_info.fm:gsbuscfg0_usage,"Usage of Global SoC Bus Configuration Register 0 (GSBUSCFG0)"</link> section in the <link:ext>DWC_usb31_programming:Title,Programming Guide</link>
   - <link:ext>DWC_usb31_databook:sys_bus_int,"System Bus Interface"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>

Global SoC Bus Configuration Register 1
  
  xHCI Register Power-On Value:
  
  If you are using a standard xHCI host driver, make sure to set the register's power-on value during coreConsultant configuration (DWC_USB31_GSBUSCFG1_INIT parameter) because the standard xHCI driver does not access this register.
  
  For more details on this register, refer to the following section:
   - <link:ext>DWC_usb31_databook:sys_bus_int,"System Bus Interface"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>

Global Tx Threshold Control Register
   Note:
   - GTXTHRCFG register is not applicable for Debug Target.
   - For more information on threshold settings, see the <link:ext>DWC_usb31_databook:rx_tx_threshold,"Rx and Tx Threshold Settings"</link> section in the Databook.

Global Rx Threshold Control Register
  
  There is an issue when ACK TP with NumP=0 followed by ACK TP with NumP=1 without ERDY TP sent by the device controller during a Burst BULK OUT transfer. This may cause third-party 3.0 host controllers to keep waiting for the ERDY TP.
  
  The USB 3.0 Specification states that "When an endpoint is not in a flow control condition, it shall not send an ERDY TP unless the endpoint is a Bulk endpoint that supports streams." In this case, after the device sent the ACK TP (nump=1), the endpoint was not in the flow control, so it did not send an ERDY.
  
  The device would have sent ERDY if the next OUT packet was not received. When the next OUT packet was received, at that time there was enough buffer space to accept it, so the device accepted the packet by informing host that it is no longer in the flow control. The Host should wait for the responses for all the OUT packets to return and then decide if the endpoint is still in flow control or not.
  
  The USB 3.1 Specification supersedes all the USB 3.0 specification. The errata states that "If the host continues, or resumes, transactions to an endpoint, the endpoint shall re-evaluate its flow control state and respond appropriately." However, there are no ECNs on the USB 3.0 for this issue.
  
  To work around this issue, the Global Rx Threshold mode must be disable by setting GRXTHRCFG.UsbRxPktCntSel = '0'. Instead, software can program the DCFG.NUMP mode (where fixed NUMP is transmitted always) instead of the RX threshold based nump mode to prevent the device from sending ACK TP with NumP=0. The NUMP in the ACK TP is the minimum value of (DCFG.NUMP, bMaxBurstSize) for each endpoint.
  
  IN Transfer Concurrency: When threshold mode is enabled, the Host controller disables IN transfer concurrency. The Host controller will execute IN transfers to one endpoint at a time in order to adhere to the maximum throughput limit specified by the threshold settings.
  
  Note:
   - GRXTHRCFG register is not applicable for Debug Target.
   - For more information on threshold settings, see the <link:ext>DWC_usb31_databook:rx_tx_threshold,"Rx and Tx Threshold Settings"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>.

Global Core Control Register
  
  Refer to <workspace>/src/DWC_usb31_params.svh for details on `DWC_USB31_GCTL_INIT.
  

Global Power Management Status Register
  
  This debug register gives information on which event caused the hibernation exit. It provides internal status and state machine information, and is for Synopsys use only for debugging purposes.

Global Status Register

Global User Control Register 1

IP NAME REGISTER
  
  This is a read-only register that contains the SYNOPSYS IP NAME

Global General Purpose Input/Output Register
  
  The application can use this register for general purpose input and output ports or for debugging.

Global User ID Register
  
  This is a read/write register containing the User ID. The power-on value for this register is specified as the User Identification Register. Power-on value during coreConsultant configuration (parameter DWC_USB31_USERID). This register can be used in the following ways:
   - To store the version or revision of your system;
   - To store hardware configurations that are outside the controller;
   - As a scratch register.

Global User Control Register
  
  This register provides a few options for the software to control the controller behavior in Host mode.

Global SoC Bus Error Address Register - Low
  
  When the AHB or AXI Master Bus returns an "Error" response, the "SoC Bus Error" is generated. In the Host mode, the host_system_err port indicates this condition. In addition, it is also indicated in the USBSTS.HSE field. In the Device mode, the GSTS.BusErrAddrVld field is the only indication of the SoC Bus Error.
  
  Note for AXI configuration:
  
  Due to the nature of AXI, it is possible that multiple AXI transactions are active at a time. The DWC_usb31 controller does not keep track of the start address of all outstanding transactions. Instead, it keeps track of the start address of the DMA transfer associated with all active transactions. It is this address that is reported in the GBUSERRADDR when a bus error occurs.
  
  For example, if the DWC_usb31 controller initiates a DMA transfer to write 1k of packet data starting at buffer address 0xABCD0000, and this DMA is broken up into multiple 256B bursts on the AXI, then if a bus error occurs on any of these associated AXI transfers, the GBUSERRADDR reflects the DMA start address of 0xABCD0000 regardless of which AXI transaction received the error.

Global SoC Bus Error Address Register - High
  
  When the AHB or AXI Master Bus returns an "Error" response, the "SoC Bus Error" is generated. In the Host mode, the host_system_err port indicates this condition. In addition, it is also indicated in the USBSTS.HSE field. In the Device mode, the GSTS.BusErrAddrVld field is the only indication of the SoC Bus Error.
  
  Note for AXI configuration:
  
  Due to the nature of AXI, it is possible that multiple AXI transactions are active at a time. The DWC_usb31 controller does not keep track of the start address of all outstanding transactions. Instead, it keeps track of the start address of the DMA transfer associated with all active transactions. It is this address that is reported in the GBUSERRADDR when a bus error occurs.
  
  For example, if the DWC_usb31 controller initiates a DMA transfer to write 1k of packet data starting at buffer address 0xABCD0000, and this DMA is broken up into multiple 256B bursts on the AXI, then if a bus error occurs on any of these associated AXI transfers, the GBUSERRADDR reflects the DMA start address of 0xABCD0000 regardless of which AXI transaction received the error.

Global ESS Port to Bus Instance Mapping Register - Low
  
  This register specifies the Enhanced SuperSpeed USB instance number to which each USB 3.1 port is connected. Synopsys coreConsultant power-on initialization value evenly distributes the USB 3.1 ports among all ESS USB instances. Software can program this register to specify how USB 3.1 ports are connected to ESS USB instances.
  
  For a configuration with the number of USB 3.1 ports same as the number of ESS Bus Instances, the remapping should not be performed during a debug session. If remapping is performed for some reason, then the debug host must be connected to a port which has a dedicated ESS Bus Instance.
  
  For example, if DWC_USB31_HOST_NUM_U3_ROOT_PORTS=3 and DWC_USB31_NUM_ESS_USB_INSTANCES=3, and software maps the first ESS port to the first ESS BI and the second/third port to the second BI, then the debug host can be connected to the first port only.
  
  The reset value for each field in the GPRTBIMAP register, which is {GPRTBIMAPHI,GPRTBIMAPLO} register is calculated as shown below:
  
  for (i=0; i<`DWC_USB31_HOST_NUM_U3_ROOT_PORTS; i=i+1)
  
  GPRTBIMAP[4*i+3:4*i] = i%`DWC_USB31_NUM_ESS_USB_INSTANCES;
  
  Note: 
   - Register fields are read-write with respect to number of port instantiated.
   - For ex. If DWC_USB31_HOST_NUM_U3_ROOT_PORTS==3, then GPRTBIMAPLO[11:0] i.e. fields (BINUM1/BINUM2/BINUM3) are read-write and all remaining fields are read-only.
   - GPRTBIMAP register is not applicable for USB 2.0-only mode.

Global ESS Port to Bus Instance Mapping Register - High
  
  This register specifies the Enhanced SuperSpeed USB instance number to which each USB 3.1 port is connected. Synopsys coreConsultant power-on initialization value evenly distributes the USB 3.1 ports among all ESS USB instances. Software can program this register to specify how USB 3.1 ports are connected to ESS USB instances.
  
  For a configuration with the number of USB 3.1 ports same as the number of ESS Bus Instances, the remapping should not be performed during a debug session. If remapping is performed for some reason, then the debug host must be connected to a port which has a dedicated ESS Bus Instance.
  
  For example, if DWC_USB31_HOST_NUM_U3_ROOT_PORTS=3 and DWC_USB31_NUM_ESS_USB_INSTANCES=3, and software maps the first ESS port to the first ESS BI and the second/third port to the second BI, then the debug host can be connected to the first port only.
  
  The reset value for each field in the GPRTBIMAP register, which is {GPRTBIMAPHI,GPRTBIMAPLO} register is calculated as shown below:
  
  for (i=0; i<`DWC_USB31_HOST_NUM_U3_ROOT_PORTS; i=i+1)
  
  GPRTBIMAP[4*i+3:4*i] = i%`DWC_USB31_NUM_ESS_USB_INSTANCES;
  
  Note: 
   - Register fields are read-write with respect to number of port instantiated. 
   - For ex. If DWC_USB31_HOST_NUM_U3_ROOT_PORTS==11, then GPRTBIMAPHI[11:0] i.e. fields (BINUM9/BINUM10/BINUM11) are read-write and all remaining fields are read-only.
   - GPRTBIMAP register is not applicable for USB 2.0-only mode.

Global Hardware Parameters Register 0
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab. 
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Hardware Parameters Register 1
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Hardware Parameters Register 2
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Hardware Parameters Register 3
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the Databook. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Hardware Parameters Register 4
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Hardware Parameters Register 5
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Hardware Parameters Register 6
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Hardware Parameters Register 7
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global Debug Queue/FIFO Space Available Register

Global BMU Control Register

Global Debug BMU Register

Global Debug LSP MUX Register in host mode
  
  This register is for internal use only.

Global Debug LSP Register
  
  This register is for internal use only.

Global Debug Endpoint Information Register 0
  
  This register is for internal use only.

Global Debug Endpoint Information Register 1
  
  This register is for internal use only.

Global High-Speed Port to Bus Instance Mapping Register - Low
  
  This register specifies the High Speed USB instance number to which each USB 3.1 port is connected. Synopsys coreConsultant power-on initialization value evenly distributes the USB 3.1 ports among all HS USB instances. The software can program this register to specify how USB 3.1 ports are connected to HS USB instances.
  
  The Reset Value for each field in the GPRTBIMAP_HS register, which is {GPRTBIMAP_HSHI,GPRTBIMAP_HSLO} register is calculated as shown below:
  for (i=0; i<`DWC_USB31_HOST_NUM_U2_ROOT_PORTS; i=i+1)
  GPRTBIMAP_HS[4*i+3:4*i] = i%`DWC_USB31_NUM_HS_USB_INSTANCES;
  
  Note:
   - Register fields are read-write with respect to number of port instantiated. 
   - For ex. If DWC_USB31_HOST_NUM_U2_ROOT_PORTS==3, then GPRTBIMAP_HSLO[11:0] i.e. fields (BINUM1/BINUM2/BINUM3) are read-write and all remaining fields are read-only.
  

Global High-Speed Port to Bus Instance Mapping Register - High
  
  This register specifies the High Speed USB instance number to which each USB 3.1 port is connected. Synopsys coreConsultant power-on initialization value evenly distributes the USB 3.1 ports among all HS USB instances. The software can program this register to specify how USB 3.1 ports are connected to HS USB instances.
  
  The Reset Value for each field in the GPRTBIMAP_HS register is calculated as shown below:
  for (i=0; i<`DWC_USB31_HOST_NUM_U2_ROOT_PORTS; i=i+1)
  GPRTBIMAP_HS[4*i+3:4*i] = i%`DWC_USB31_NUM_HS_USB_INSTANCES;
  
  Note:
   - Register fields are read-write with respect to number of port instantiated. 
   - For ex. If DWC_USB31_HOST_NUM_U2_ROOT_PORTS==3, then GPRTBIMAP_HSHI[11:0] i.e. fields (BINUM9/BINUM10/BINUM11) are read-write and all remaining fields are read-only.
  

Global Full/Low-Speed Port to Bus Instance Mapping Register - Low
  
  This register specifies the Full/Low Speed USB instance number to which each USB 3.1 port is connected. Synopsys coreConsultant power-on initialization value evenly distributes the USB 3.1 ports among all FS/LS USB instances. Software can program this register to specify how USB 3.1 ports are connected to FS/LS USB instances
  
  The Reset Value for each field in the GPRTBIMAP_FS register, which is {GPRTBIMAP_FSHI,GPRTBIMAP_FSLO} register is calculated as shown below:
  for (i=0; i<`DWC_USB31_HOST_NUM_U2_ROOT_PORTS; i=i+1)
  GPRTBIMAP_FS[4*i+3:4*i] = i%`DWC_USB31_NUM_FSLS_USB_INSTANCES;
  
  Note:
   - Register fields are read-write with respect to number of port instantiated. 
   - For ex. If DWC_USB31_HOST_NUM_U2_ROOT_PORTS==3, then GPRTBIMAP_FSLO[11:0] i.e. fields (BINUM1/BINUM2/BINUM3) are read-write and all remaining fields are read-only.
  

Global Full/Low-Speed Port to Bus Instance Mapping Register - High
  
  This register specifies the Full/Low Speed USB instance number to which each USB 3.1 port is connected. Synopsys coreConsultant power-on initialization value evenly distributes the USB 3.1 ports among all FS/LS USB instances. Software can program this register to specify how USB 3.1 ports are connected to FS/LS USB instances
  
  The Reset Value for each field in the GPRTBIMAP_FS register, which is {GPRTBIMAP_FSHI,GPRTBIMAP_FSLO} register is calculated as shown below:
  for (i=0; i<`DWC_USB31_HOST_NUM_U2_ROOT_PORTS; i=i+1)
  GPRTBIMAP_FS[4*i+3:4*i] = i%`DWC_USB31_NUM_FSLS_USB_INSTANCES;
  
  Note:
   - Register fields are read-write with respect to number of port instantiated. 
   - For ex. If DWC_USB31_HOST_NUM_U2_ROOT_PORTS==3, then GPRTBIMAP_FSHI[11:0] i.e. fields (BINUM9/BINUM10/BINUM11) are read-write and all remaining fields are read-only.
  

Global Host Mode SoC Bandwidth Override Register

USB31 IP VERSION
   -  This register reflects the current corekit release number in ASCII format

USB31 IP VERSION TYPE
   -  This register reflects the current release type of the IP

Global System Bus Blocking Window Control

Global PCIe L1 exit Latency Register

Global Hardware Parameters Register 8
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.

Global SMAC CONTROL REGISTER

Global User Control Register 2

Global User Control Register 3

Global Device TXFIFO DMA Priority Register
  
  This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high, 0: low) of each TXFIFO[n]. When multiple TXFIFOs compete for DMA service at a given time (that is, multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner:
   - 1. High-priority TXFIFOs are granted access using round-robin arbitration
   - 2. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full).
  For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed.
  
  When configuring periodic IN endpoints, software must set register bit[n]=1, where n is the TXFIFO assignment. This ensures that the DMA for isochronous or interrupt IN endpoints are prioritized over bulk or control IN endpoints.
  
  This register is present only when the controller is configured to operate in the device mode (includes DRD). The register size corresponds to the number of Device IN endpoints.
  
  Note
   - Since the device mode uses only one RXFIFO, there is no Device RXFIFO DMA Priority Register.

Global Host TXFIFO DMA Priority Register (GTXFIFOPRIHST)
  
  This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the priority (1: high, 0: low) of TXFIFO[n] within a speed group. When multiple TXFIFOs compete for DMA service at a given time (i.e., multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner:
   - 1. Among the FIFOs in the same speed group (SS or HS/FSLS): 
   a. High-priority TXFIFOs are granted access using round-robin arbitration 
   b. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full).
   - 2. The TX DMA arbiter prioritizes the SS speed group or HS/FSLS speed group according to the ratio programmed in the GDMAHLRATIO register.
  For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed.
  
  This register is present only when the controller is configured to operate in the host mode (includes DRD). The register size corresponds to the number of configured USB bus instances; for example, in the default configuration, there are 3 USB bus instances (1 SS, 1 HS, and 1 FSLS).

Global Host RXFIFO DMA Priority Register
  
  This register specifies the relative DMA priority level among the Host RXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the priority (1: high, 0: low) of RXFIFO[n] within a speed group. When multiple RXFIFOs compete for DMA service at a given time (i.e., multiple RXQs contain RX DMA requests and their corresponding RXFIFOs have data available), the RX DMA arbiter grants access on a packet-basis in the following manner:
   - 1. Among the FIFOs in the same speed group (SS or HS/FSLS): 
   a. High-priority RXFIFOs are granted access using round-robin arbitration 
   b. Low-priority RXFIFOs are granted access using round-robin arbitration only after high-priority RXFIFOs have no further processing to do (that is, either the RXQs are empty or the corresponding RXFIFOs do not have the required data).
   - 2. The RX DMA arbiter prioritizes the SS speed group or HS/FSLS speed group according to the ratio programmed in the GDMAHLRATIO register.
  For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed.
  
  This register is present only when the controller is configured to operate in the host mode (includes DRD). The register size corresponds to the number of configured USB bus instances; for example, in the default configuration, there are 3 USB bus instances (1 SS, 1 HS, and 1 FSLS).

Global Host Debug Capability DMA Priority Register
  
  This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and TXFIFO DMA priority registers, when the DbC mode is enabled.
  
  Priority settings are specified in relation to the low-priority SS speed group:
   - 1. Normal priority indicates that the DbC FIFOs are considered identical to the Host SS low-priority FIFOs.
   - 2. Low priority indicates that the DbC FIFOs are considered to have lower priority than all Host SS FIFOs.
   - 3. High priority indicates that the DbC FIFOs are considered higher priority than the Host SS low-priority FIFOs but lower priority than the Host SS high-priority FIFOs.
  This register is present only when the controller is configured to operate in Host Debug Capability (DbC) mode.

Global Host FIFO DMA High-Low Priority Ratio Register
  
  This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low Priority Ratio grants as indicated in the register separately for TX and RX.
  
  To illustrate, consider that all FIFOs are requesting access simultaneously, and the ratio is 4. SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, and so on.
  
  If FIFOs from both speed groups are not requesting access simultaneously then,
   - if SS got grants 4 out of the last 4 times, then HS/FSLS get the priority on any future request.
   - if HS/FSLS got the grant last time, SS gets the priority on the next request.
   - if there is a valid request on either SS or HS/FSLS, a grant is always awarded; there is no idle.
  This register is present if the controller is configured to operate in host mode (includes DRD).

Global Number of Async Outstanding DMA Register

Global Number of Periodic Outstanding DMA Register

Global Frame Length Adjustment Register
  This register provides options for the software to control the controller behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an option to override the fladj_30mhz_reg sideband signal. This also facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.

Global User Control Register 4

Global User Control Register 5