GSYSBLKWINCTRL 

         Global System Bus Blocking Window Control
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C1B0

Size: 32

Offset: 0xB0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

sys_blocking_ok_all_the_time

RW 0x0

disable_no_blocking_window

RW 0x0

erst_prefetching_en

RW 0x0

erst_prefetching_watermark

RW 0x0

reserved_23_16

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

end_no_blocking_time

RW 0x0

beginining_no_blocking_time

RW 0x0

GSYSBLKWINCTRL Fields

Bit Name Description Access Reset
31 sys_blocking_ok_all_the_time 
Always assert ok_to_block_sysbus=1
 RW 0x0
30 disable_no_blocking_window 
Setting this bit does not check uf_start_no_blocking_time and uf_end_no_blocking_time
 RW 0x0
29 erst_prefetching_en 
Enable ERST Entry Prefetching
  
  When enabled, the host controller will prefetch one ERST entry into the cache based on the erst_prefetching_watermark.
  
  When not enabled, the host controller will prefetch one ERST entry into the cache when the current segment has only 1 TRB left.
  
  When LPDDR4 is used, enabling this feature can avoid the corner case in which the LSP is running out of event TRB and fetching of a new ERST entry is blocked by re-training. This corner case may cause QOS issue on ISOC EPs.
  
  Enabling this feature may cause the compliant test when the event ring size is changed by the driver.
 RW 0x0
28:24 erst_prefetching_watermark 
ERST Prefetching Watermark
  
   Controls when the host controller will prefetch the next ERST entry into the cache before the current one runs out of TRBs. 
  
   Only have effect when the erst_prefetching_en set to 1. The maximum valid value is 31 
  
   When it is less than  2 (0 or 1), the event ring handler will start the prefetching of the next ERST when the current segment has only 1 TRB left   
  
   otherwise  , the ERST prefetching starts when current the current segment has the number of TRBs less than this register value 
  
   When LPDDR4 is used,  Setting erst_prefetching_en to 1 and setting this register  a larger value an avoid the corner case in which the LSP is running out of event TRB but fetching of a new ERST entry is blocked 
  
   by re-training. This corner case may cause QOS issue on ISOC EPs.
  
   Setting it to larger than 15 may cause the compliant test failure on the event ring size change test .
 RW 0x0
23:16 reserved_23_16 
Reserved
 RW 0x0
15:8 end_no_blocking_time 
System bus no blocking time window (in usec) at end of uframe. 
  Valid value: 0 to 63
 RW 0x0
7:0 beginining_no_blocking_time 
System bus no blocking time window (in usec) at start of uframe. 
  Valid value: 0 to 63
 RW 0x0