GSMACCTL 

         Global SMAC CONTROL REGISTER
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C604

Size: 32

Offset: 0x504

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dbg_tis_index

RW 0x0

dbg_ptl_addr

RW 0x0

reserved_25_8

RW 0x0

hostin_signle_en

RW 0x0

hostout_single_en

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_4

RW 0x0

single_psqdir_en

RW 0x0

host_mask_nump0

RW 0x0

ignore_babble

RW 0x0

single_TBT_req

RW 0x0

GSMACCTL Fields

Bit Name Description Access Reset
31:30 dbg_tis_index 
SMAC bus instance index
 RW 0x0
29:26 dbg_ptl_addr 
PTL debug address
 RW 0x0
25:18 reserved_25_8 
Reserved
 RW 0x0
17 hostin_signle_en 
Host: Limit a maximum of one active IN transfer on USB at a time
 RW 0x0
16 hostout_single_en 
Host: Limit a maximum of one active OUT transfer on USB at a time
 RW 0x0
15:4 reserved_15_4 
Reserved
 RW 0x0
3 single_psqdir_en 
Enable PSQ message type [PSQDIR] sorting
  
  If this bit is set, enables PSQ message sorting with PSQDIR:
  
   0: PSQDIR=0 for all messages
  
   1: PSQDIR=0 for OUT endpoints, CTRL endpoints, non-transaction headers (ie Vendor LMP)
  
      PSQDIR=1 for IN endpoints
 RW 0x0
2 host_mask_nump0 
Mask TPACK nump0 (stream) with nump1
  
  LSP workaround - for host stream transfers, if TP.ACK.nump=0 is received, then convert to nump=1 to avoid flow control
  
  If this bit is set, the controller converts TP.ACK.nump=0 to TP.ACK.nump=1.
   - 0: Normal operation
   - 1: Convert TP.ACK nump=0 to nump=1
 RW 0x0
1 ignore_babble 
Ignore Receive babble conditions
  
  When the controller receives data packets, a payload that exceeds the allowed Max Packet Size is considered a babble condition.
  
  If this bit is set, the controller ignores babble conditions.
   - 0: detect receive payload babble conditions
   - 1: ignore receive payload babble conditions
 RW 0x0
0 single_TBT_req 
Disable pipelined Transmit Data
  
  The transmit data path utilizes an internal pipeline to reduce interpacket delay during burst transmit. 
  
  Setting this bit disables the pipeline mechanism. Interpacket delay is increased if pipelining is disabled.
   - 0: enable transmit data pipelining
   - 1: disable transmit data pipelining
 RW 0x0