GDMAHLRATIO 

         Global Host FIFO DMA High-Low Priority Ratio Register
  
  This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low Priority Ratio grants as indicated in the register separately for TX and RX.
  
  To illustrate, consider that all FIFOs are requesting access simultaneously, and the ratio is 4. SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, and so on.
  
  If FIFOs from both speed groups are not requesting access simultaneously then,
   - if SS got grants 4 out of the last 4 times, then HS/FSLS get the priority on any future request.
   - if HS/FSLS got the grant last time, SS gets the priority on the next request.
   - if there is a valid request on either SS or HS/FSLS, a grant is always awarded; there is no idle.
  This register is present if the controller is configured to operate in host mode (includes DRD).
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C624

Size: 32

Offset: 0x524

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_29

RO 0x0

hstrxfifo_mac

RW 0x8

reserved_23_21

RO 0x0

hsttxfifo_mac

RW 0x8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_13

RO 0x0

hstrxfifo_dma

RW 0x1

reserved_7_5

RO 0x0

hsttxfifo_dma

RW 0x1

GDMAHLRATIO Fields

Bit Name Description Access Reset
31:29 reserved_31_29 
Reserved
 RO 0x0
28:24 hstrxfifo_mac 
RX MAC ESS Priority Count
  
   Specifies the Global Host FIFO MAC access Ratio Register's (GDMAHLRATIO) RX SS:HSFSLS Ratio power-on initialization value (bit[28:24]).
  
   This register specifies MAC write access count relation between ESS FIFOs vs HS+FSLS FIFOs. Specifically, FIFO access arbiter prioritizes the HS+FSLS FIFOs for one clock after the specified number of write access to the SS FIFOs. 
  
  Do not change the default value set by coreConsultant for your configuration.
RW 0x8
23:21 reserved_23_21 
Reserved
 RO 0x0
20:16 hsttxfifo_mac 
TX MAC ESS Priority Count
  
   Specifies the Global Host FIFO MAC access Ratio Register's (GDMAHLRATIO) TX SS:HSFSLS Ratio power-on initialization value (bit[20:16]).
  
   This register specifies MAC read access count relation between ESS FIFOs vs HS+FSLS FIFOs. Specifically, FIFO read access arbiter prioritizes the HS+FSLS FIFOs for one clock after the specified number of read access to the SS FIFOs. 
  
  Do not change the default value set by coreConsultant for your configuration.
RW 0x8
15:13 reserved_15_13 
Reserved
 RO 0x0
12:8 hstrxfifo_dma 
RX DMA ESS Priority Count
  
   Specifies the Global Host FIFO DMA access Ratio Register's (GDMAHLRATIO) RX SS:HSFSLS Ratio power-on initialization value (bit[12:8]).
  
   This register specifies the relative priority of the SS FIFOs vs. the HS+FSLS FIFOs. Specifically, the DMA arbiter prioritizes the HS/FSLS round-robin arbiter group for one packet after the specified number of packet grants to the ESS round-robin arbiter group. For more information, see the "GDMAHLRATIO" section in the <link:ext>DWC_usb31_databook:Title,Databook</link>.
  
   When a standard driver is used, such as the xHCI driver from Microsoft, this register must be initialized to meet system requirements before synthesizing the controller.
  
   If you are developing your own xHCI host driver, then this register can be configured by your driver. It is recommended to keep this value as 1 so that HS/FSLS gets same priority as ESS. The HS/FSLS bandwidth requirement is negligible compared to ESS, so keeping this value as 1 ensures USB 2.0 operation is not affected by high bandwidth ESS.
   - Enabled : (DWC_USB31_MODE == 1 || DWC_USB31_MODE == 2) && DWC_USB31_MBUS_TYPE!=4 && (DWC_USB31_EN_USB2_ONLY==0)
RW 0x1
7:5 reserved_7_5 
Reserved
 RO 0x0
4:0 hsttxfifo_dma 
TX DMA ESS Priority Count
  
   Specifies the Global Host FIFO DMA access Ratio Register's (GDMAHLRATIO) TX SS:HSFSLS Ratio power-on initialization value (bit[4:0]).
  
   This register specifies the access weight of the SS FIFOs vs. the HS+FSLS FIFOs. Specifically, the DMA arbiter prioritizes the HS/FSLS round-robin arbiter group for one packet after the specified number of packet grants to the ESS round-robin arbiter group.For more information, see the "GDMAHLRATIO" section.
  
   When a standard driver is used, such as the xHCI driver from Microsoft, this register must be initialized to meet system requirements before synthesizing the controller.
  
   If you are developing your own xHCI host driver, then this register can be configured by your driver. It is recommended to keep this value as 1 so that HS/FSLS gets same priority as ESS. The HS/FSLS bandwidth requirement is negligible compared to ESS, so keeping this value as 1 ensures USB 2.0 operation is not affected by high bandwidth ESS.
   -Enabled : (DWC_USB31_MODE == 1 || DWC_USB31_MODE == 2) && DWC_USB31_MBUS_TYPE!=4 && (DWC_USB31_EN_USB2_ONLY==0)
RW 0x1