GDBGFIFOSPACE

         Global Debug Queue/FIFO Space Available Register


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100C100`	`0x1100C160`

Size: 32

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`SPACE_AVAILABLE` `RO 0x43`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_15_9` `RO 0x0`							`FIFO_QUEUE_SELECT` `RW 0x0`

GDBGFIFOSPACE Fields

Bit Name Description Access Reset

31:16

Bit	Name	Description	Access	Reset
31:16	`SPACE_AVAILABLE`	SPACE_AVAILABLE	`RO`	`0x43`
15:9	`reserved_15_9`	Reserved_15_9	`RO`	`0x0`
8:0	`FIFO_QUEUE_SELECT`	FIFO/Queue Select - FIFO/Queue Select[8:5] indicates the FIFO/Queue Type - FIFO/Queue Select[4:0] indicates the FIFO/Queue Number For example, 9'b0_0010_0001 refers to RxFIFO_1 and 9'b0_0101_1110 refers to TxReqQ_30. - 9'b0_0001_1111 to 9'b0_0000_0000: TxFIFO_31 to TxFIFO_0 - 9'b0_0011_1111 to 9'b0_0010_0000: RxFIFO_31 to RxFIFO_0 - 9'b0_0101_1111 to 9'b0_0100_0000: TxReqQ_31 to TxReqQ_0 - 9'b0_0111_1111 to 9'b0_0110_0000: RxReqQ_31 to RxReqQ_0 - 9'b0_1001_1111 to 9'b0_1000_0000: RxInfoQ_31 to RxInfoQ_0 - 9'b0_1010_0000: DescFetchQ_0 (for backwards compatibility) - 9'b0_1010_0001: EventQ_0 (for backwards compatibility) - 9'b0_1010_0010: ProtocolStatusQ_0 - 9'b0_1101_1111 to 9'b0_1110_0000: DescFetchQ_31 to DescFetchQ_0 - 9'b0_1111_1111 to 9'b0_1110_0000: WriteBack/EventQ_31 to WriteBack/EventQ_0 - 9'b1_0000_0111 to 9'b1_0000_0000: AuxEventQ_7 to AuxEventQ_0 (if EN_SEPARATE_DESC_QUEUES=1	`RW`	`0x0`

SPACE_AVAILABLE

SPACE_AVAILABLE

RO

0x43

15:9

reserved_15_9

Reserved_15_9

RO

0x0

8:0

FIFO_QUEUE_SELECT

FIFO/Queue Select 
   - FIFO/Queue Select[8:5] indicates the FIFO/Queue Type
   - FIFO/Queue Select[4:0] indicates the FIFO/Queue Number
  For example, 9'b0_0010_0001 refers to RxFIFO_1 and 9'b0_0101_1110 refers to TxReqQ_30.
   - 9'b0_0001_1111 to 9'b0_0000_0000: TxFIFO_31 to TxFIFO_0
   - 9'b0_0011_1111 to 9'b0_0010_0000: RxFIFO_31 to RxFIFO_0
   - 9'b0_0101_1111 to 9'b0_0100_0000: TxReqQ_31 to TxReqQ_0
   - 9'b0_0111_1111 to 9'b0_0110_0000: RxReqQ_31 to RxReqQ_0
   - 9'b0_1001_1111 to 9'b0_1000_0000: RxInfoQ_31 to RxInfoQ_0
   - 9'b0_1010_0000: DescFetchQ_0 (for backwards compatibility)
   - 9'b0_1010_0001: EventQ_0 (for backwards compatibility)
   - 9'b0_1010_0010: ProtocolStatusQ_0
   - 9'b0_1101_1111 to 9'b0_1110_0000: DescFetchQ_31 to DescFetchQ_0
   - 9'b0_1111_1111 to 9'b0_1110_0000: WriteBack/EventQ_31 to WriteBack/EventQ_0
   - 9'b1_0000_0111 to 9'b1_0000_0000: AuxEventQ_7 to AuxEventQ_0 (if EN_SEPARATE_DESC_QUEUES=1

RW

0x0