GUCTL1

DEV_DECOUPLE_L1L2_EVT
  Enable this bit if you want to use L1 (LPM) events separately and not combine it with L2 events when operating in USB 2.0 speeds.
   - 0: L1 and L2 events (suspend and resume) are not separated. For both L1 and L2 events, common suspend and resume events are generated. 
   - 1: L1 and L2 events are separated when operating in USB 2.0 mode. For L1 and L2 events, separate suspend and resume events are generated.

DS_RXDET_MAX_TOUT_CTRL
  
  This bit is used to control the tRxDetectTimeoutDFP timer for the Enhanced SuperSpeed link.
   - 0: 12ms is used as tRxDetectTimeoutDFP
   - 1: 120ms is used as the tRxDetectTimeoutDFP
  This bit is used only in host mode. For more details, refer to the USB 3.1 Specification.
  

FILTER_SE0_FSLS_EOP
   - 0: Single sampling (utmi/ulpi clock) of linestate is checked for SE0 detection.
   - 1: Feature enabled; Two samplings of linestate are checked for SE0 detection
  This bit is applicable for FS/LS operation. If this feature is enabled, SE0 on the linestate is validated for two consecutive utmi/ulpi clock edges for EOP detection. This feature is applicable only in FS in device mode and FS/LS mode of operation in host mode. 
   - Device mode (FS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then for device LPM handshake, the controller ignores single SE0 glitch on the linestate during transmit. Only two or more SE0 is considered as a valid EOP on FS port.
   - Host mode (FS/LS): If GUCTL1.FILTER_SE0_FSLS_EOP is set, then the controller ignores single SE0 glitch on the linestate during transmit. Only two or more SE0 is considered as a valid EOP on FS/LS port.
  Enable this feature if linestate has SE0 glitches during transmission. This bit is quasi-static, that is, it must not be changed during operation. 
  

TX_IPGAP_LINECHECK_DIS
   - 0: The linestate transitioning from J to idle for HS mode treated as end of current packet.
   - 1: Feature enabled; For detecting the HS end of packet, a fixed delay is used instead of linestate transition.
  This bit is applicable for HS operation of U2MAC. If this feature is enabled, then the 2.0 MAC operating in HS ignores the UTMI/ULPI linestate during transmission of a token (during token-to-token and token-to-data IPGAP). When enabled, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during this time. This feature is applicable only in HS mode of operation. 
   - Device mode: If GUCTL1.TX_IPGAP_LINECHECK_DIS is set, then for device LPM handshake, the controller ignores the linestate after TX and waits for a fixed number of clocks (40 bit times equivalent) after transmitting ACK on utmi.
   - Host mode: If GUCTL1.TX_IPGAP_LINECHECK_DIS is set, then the ipgap (between token to token/data) is added by 40 bit times of TXENDDELAY, and linestate is ignored during this 40 bit times delay.
  Enable this bit if linestate does not reflect the expected line state (J) during transmission. This bit is quasi-static, that is, it must not be changed during operation. 
  

DEV_TRB_OUT_SPR_IND
   - 0: Feature disabled; OUT TRB status does not set the Short Packet received bit
   - 1: Feature enabled; OUT TRB status indicates Short Packet
  This bit is applicable for device mode only (and ignored in host mode). This feature can be enabled if the device application (software/hardware) wants to know whether a short packet is received for an OUT in the TRB status itself, so that a bit is set in the TRB writeback in the buf_size dword. Bit[26] - SPR of the {trbstatus, RSVD, SPR, PCM1, bufsize} dword will be set during an OUT transfer TRB write back if this is the last TRB used for that transfer descriptor. This bit is quasi-static, that is, it must not be changed during device operation. 
  

Reserved

Reserved

DEV_L1_EXIT_BY_HW
   - 0: Disables device L1 hardware exit logic
   - 1: Feature enabled
  This bit is applicable for device mode (2.0) only. This field enables device controller sending remote wakeup for L1 if the device becomes ready for sending/accepting data when in L1 state.
  If the host expects the device to send remote wakeup signaling to resume after going into L1 in flow controlled state, then this bit can be set to send the remote wake signal automatically when the device controller becomes ready.
  This hardware remote wake feature is applicable only to bulk and interrupt transfers, and not for Isoch/Control
   - When control transfers are in progress, the LPM will be rejected (NYET response).  Only after control transfers are completed (either with ACK/STALL), LPM will be accepted
   - For Isoch transfers, the host needs to do the wake-up  and start the transfer. Device controller will not do remote-wakeup when Isoch endpoints get ready. The device SW needs to keep the GUSB2PHYCFG[EnblSlpM] reset in order to keep the PHY clock to be running for keeping track of SOF intervals.
   - When L1 hibernation is enabled, the controller will not do automatic exit for hibernation requests through L1.
  This bit is quasi-static, it must not be changed during device operation. 
  

This register field is used to add on to the default inter packet gap setting in the USB 2.0 MAC. 
  
  It should be programmed to a non-zero value only in case where you need to increase the default inter packet delay calculations in the USB 2.0 MAC module ${ldsg}_u2mac.v
  The inter packet delay is increased by number of utmi/ulpi clock cycles of this field value.
  

Reserved

Reserved

Disable hardware LPM capability in the xHCI capability register.
  
  When set, it disables hardware LPM capability in xHCI capability register.

Disable hardware LPM function in all USB 2.0 ports.
  
  When set, it disables hardware LPM function in all USB 2.0 ports.

Disable ref_clk gating for USB 2.0 PHY (DisUSB2RefClkGtng)
  
  If ref_clk gating is disabled, then the ref_clk input cannot be turned off to the USB 2.0 PHY and controller. This is independent of the GCTL[DisClkGtng] setting.
   - 1'b0: ref_clk gating enabled for USB 2.0 PHY
   - 1'b1: ref_clk gating disabled for USB 2.0 PHY

Disable ref_clk gating (DisRefClkGtng
  
  If the ref_clk gating is disabled then input ref_clk cannot be turned off to SSPHY and controller. This is independent of GCTL[DisClkGtng] setting.
   - 1'b0: ref_clk gating Enabled for SSPHY
   - 1'b1: ref_clk gating Disabled for SSPHY

RESUME_OPMODE_HS_HOST
  
  This bit is used only in host mode, and is for 2.0 opmode behaviour in HS Resume.
   - When this bit is set to '1', the utmi/ulpi opmode will be changed to "normal" along with HS terminations after EOR. This is to support certain legacy UTMI/ULPI PHYs.
   - When this bit is set to '0', the utmi/ulpi opmode will be changed to "normal" 2us after HS terminations change after EOR.

Reserved

L1_SUSP_THRLD_EN_FOR_HOST
  
  This bit is used only in host mode.
  
  The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals (see Table 5-18 on page 363) as follows:
  
  The controller asserts the utmi_l1_suspend_n signal to put the PHY into deep low-power mode in L1 when both of the following are true:
   - The device accepted BESL/BESLD value is greater than or equal to the value in L1_SUSP_THRLD_FOR_HOST field.
   - The L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1'b1.
  The controller asserts utmi_sleep_n on L1 when one of the following is true:
   - The device accepted BESL/BESLD value is less than the value in L1_SUSP_THRLD_FOR_HOST field.
   - The L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1'b0.

L1_SUSP_THRLD_FOR_HOST
  
  This field is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1. For more details, refer to the description of the L1_SUSP_THRLD_EN_FOR_HOST bit.
  
  Note: Program this register field based on the UTMI/ULPI wakeup time in L1 suspend/sleep. In addition, for PCIe-based implementation, consider the DBESLD register value also.

Host ELD Enable (HELDEn)
  
  When this bit is set to 1, it enables the Exit Latency Delta (ELD) support defined in the xHCI 1.1.
  
  This bit is used only in the host mode. This bit has to be set to 1 in Host mode.

Host Parameter Check Disable (HParChkDisable)
  
  When this bit is set to '0', the xHC checks that the input slot/EP context fields comply to the xHCI Specification. Upon detection of a parameter error during command execution, the xHC generates an event TRB with completion code indicating 'PARAMETER ERROR'.
  
  When the bit is set to '1', the xHC does not perform parameter checks and does not generate 'PARAMETER ERROR' completion code.

Reserved

LOA_FILTER_EN
  
  If this bit is set, the USB 2.0 port babble is checked at least three consecutive times before the port is disabled. This prevents false triggering of the babble condition when using low quality cables.
  
  Note: This bit is valid only in host mode.