GPCIEL1EXTLAT

         Global PCIe L1 exit Latency Register


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100C100`	`0x1100C1B4`

Size: 32

Offset: 0xB4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`pcie_l1_exit_mode_ctrl` `RW 0x0`		`reserved_29_12` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_29_12` `RO 0x0`				`pcie_l1_exit_latency` `RW 0x0`

GPCIEL1EXTLAT Fields


Bit	Name	Description	Access	Reset
31:30	`pcie_l1_exit_mode_ctrl`	pcie_l1_exit_mode_ctrl	`RW`	`0x0`
29:12	`reserved_29_12`	Reserved	`RO`	`0x0`
11:0	`pcie_l1_exit_latency`	pcie_l1_exit_latency This is the time (in usec) the PCIe bus needed to be waked up from L1 and resume normal operation Valid value: 0-125	`RW`	`0x0`