GTXFIFOPRIHST

         Global Host TXFIFO DMA Priority Register (GTXFIFOPRIHST)
  
  This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the priority (1: high, 0: low) of TXFIFO[n] within a speed group. When multiple TXFIFOs compete for DMA service at a given time (i.e., multiple TXQs contain TX DMA requests and their corresponding TXFIFOs have space available), the TX DMA arbiter grants access on a packet-basis in the following manner:
   - 1. Among the FIFOs in the same speed group (SS or HS/FSLS): 
   a. High-priority TXFIFOs are granted access using round-robin arbitration 
   b. Low-priority TXFIFOs are granted access using round-robin arbitration only after the high-priority TXFIFOs have no further processing to do (that is, either the TXQs are empty or the corresponding TXFIFOs are full).
   - 2. The TX DMA arbiter prioritizes the SS speed group or HS/FSLS speed group according to the ratio programmed in the GDMAHLRATIO register.
  For scatter-gather packets, the arbiter grants successive DMA requests to the same FIFO until the entire packet is completed.
  
  This register is present only when the controller is configured to operate in the host mode (includes DRD). The register size corresponds to the number of configured USB bus instances; for example, in the default configuration, there are 3 USB bus instances (1 SS, 1 HS, and 1 FSLS).