GBMUCTL 

         Global BMU Control Register
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C164

Size: 32

Offset: 0x64

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_16

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_6

RO 0x0

separate_psq_en

RW 0x1

reserved_4_3

RO 0x0

axi_storder_en

RW 0x1

active_id_en

RW 0x1

reserved_0

RW 0x0

GBMUCTL Fields

Bit Name Description Access Reset
31:16 reserved_31_16 
Reserved
 RW 0x0
15:6 reserved_15_6 
Reserved
 RO 0x0
5 separate_psq_en 
When DWC_USB31_EN_SEPARATE_PSQ_PER_DIR is enabled Separate internal process queue and state machine per direction is enabled
  
   when the bit is set to ‘1’, BMU will process the plr_msg_type[PSQ_DIR] bit and pushes the messages to separate PSQ based on direction including special handling of control endpoint messages.
  
   when the bit is set to ‘0’, BMU will ignore the plr_msg_type[PSQ_DIR] bit for all message types and pushes the messages to single PSQ to retain the legacy mode of operation.
RW 0x1
4:3 reserved_4_3 
Reserved
 RO 0x0
2 axi_storder_en 
When DWC_USB31_AXI_STRICT_ORDER_EN parameter is enabled, both descriptor and data RxDMAs should be configured to use non-posted commands. For a given BI, descriptor/event RxDMA won't be issued until the previous issued data RxDMA is completed on the bus
 RW 0x1
1 active_id_en 
Active Id enabled
 RW 0x1
0 reserved_0 
Reserved
 RW 0x0