GUCTL3 

         Global User Control Register 3
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C60C

Size: 32

Offset: 0x50C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31

RW 0x0

reserved_30_22

RW 0x0

CFGEP_CMD_SWITCHING_TIME_CTRL

RW 0x2

BLOCK_CONCURRENT_IN_CTRL_XFERS

RW 0x0

SSBI_SINGLE_EP_MODE_DISABLE

RW 0x0

DISEXTBUSCLKGT_U1U2L1

RW 0x0

DISEXTBUSCLKGT

RW 0x1

RSVD_PERI_BANDWIDTH_FS

RW 0x0

USB20_RETRY_DISABLE

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15

RW 0x0

reserved_14

RW 0x1

reserved_13

RW 0x0

SVC_OPP_PER_HS_SEP

RW 0xB

BARB_BURST_ENABLE

RW 0x0

INTR_EP_PING_ENABLE

RW 0x0

PERIODIC_UF_THR_FSLS

RW 0xC

GUCTL3 Fields

Bit Name Description Access Reset
31 reserved_31 
Reserved
 RW 0x0
30:25 reserved_30_22 
Reserved
 RW 0x0
24:22 CFGEP_CMD_SWITCHING_TIME_CTRL 
Configure EP command switching time control
  
  Bit 24 : Enable the fast EP configure mode
   - 1: fast EP configure enabled . Only consider the ISOC EP service interval in determining the switching time
   - 0: fast EP configure disabled. Consider the ISOC and INTR EP service interval in determining the switching time
  Bit [23:22] Maximum switching frame boundary
   - 2’b00 :   Maximum Switching Frame boundary is 32ms . Fast EP configure enabled/disbled based on bit 24  guctl3[24:22]='b000 is legacy switching mode
   - 2’b01 :   Maximum Switching Frame boundary is 1ms . Fast EP configure enabled/disbled based on bit 24
   - 2’b10 :   Maximum Switching Frame boundary is 4ms . Fast EP configure enabled/disbled based on bit 24
   - 2’b11 :   Maximum Switching Frame boundary is 8ms . Fast EP configure enabled/disbled based on bit 24
 RW 0x2
21 BLOCK_CONCURRENT_IN_CTRL_XFERS 
Block concurrent IN transactions during Control transfers
  
  This bit controls the way in which concurrent IN is handled for control transfers
   - 0: Concurrent IN transfers are blocked during control transfers
   - 1: Concurrent IN transfers are not blocked during control transfers
 RW 0x0
20 SSBI_SINGLE_EP_MODE_DISABLE 
SS BI Single EP mode Disable 
  
  When set, this field disables single EP mode in the SS BI.
   - 1'b0: Single EP mode in SS BI enabled
   - 1'b1: Single EP mode in SS BI disabled
RW 0x0
19 DISEXTBUSCLKGT_U1U2L1 
Disable External Bus Clock Gating in U1/U2/L1 state
  
  This bit is only used when the DWC_USB31_EXT_BUS_CLK_OFF parameter is set to 1. This bit is used to generate the pmgt_ext_bus_clk_off signal when the following conditions occur:
   -  GUCTL3[DISEXTBUSCLKGT] is cleared
   -  GUCTL3[DISEXTBUSCLKGT_U1U2L1] is cleared
   -  Link is in RXDET, DISABLE, INACTIVE, or U3 state and the controller is idle 
   -  All USB 2.0 ports are in L2 state, that is, UTMI suspend is asserted
 RW 0x0
18 DISEXTBUSCLKGT 
Disable External Bus Clock Gating
  
  This bit is only used when the DWC_USB31_EXT_BUS_CLK_OFF parameter is set to 1. This bit is used to generate the pmgt_ext_bus_clk_off signal when the following conditions occur:
   -  GUCTL3[DISEXTBUSCLKGT] is cleared
   -  Link is in RXDET, DISABLE, INACTIVE, U1, U2, or U3 state and the controller is idle 
   -  All USB 2.0 ports are in LPM-L1 or L2 state, that is, UTMI suspend, l1_suspend and sleep is asserted
 RW 0x1
17 RSVD_PERI_BANDWIDTH_FS 
85percent bandwidth reservation for periodic transfer for FS bus behind HS hub
  
   When not set, the bandwidth reserved for periodic transfers on a FS bus behind a HS hub is 85% . Setting it to 1 will increase reserved bandwidth to 90% 
  
   When SSplit in uframe 7 is disabled , the bandwidth avaliable to periodic transfer is less . Setting reserved bandwith to be 90% may cause over scheduling 
   - 1'b0: 85% of FS bus bandwidth reserved for periodic transfer when the FS bus is behind HS hub
   - 1'b1: 90% of FS bus bandwidth reserved for periodic transfer when the FS bus is behind HS hub
 RW 0x0
16 USB20_RETRY_DISABLE 
USB2.0 Internal Retry Disable 
  
   When set, this field disables the internal retry feature on the USB 2.0 bus. 
   - 1'b0:  Internal retry feature enabled
   - 1'b1:  Internal retry feature disabled
 RW 0x0
15 reserved_15 
Reserved
 RW 0x0
14 reserved_14 
Reserved
  
   This Reserved bit is used internally. The default value is required to be non-zero.
RW 0x1
13 reserved_13 
Reserved
 RW 0x0
12:9 SVC_OPP_PER_HS_SEP 
Service opportunities for HS bulk endpoints in single endpoint mode 
  
  Indicates the number of Service Opportunities (SOs) that will be allocated to the HS bulk endpoint when it is the only one asynchronous endpoint active for that bus instance.
  
  A value of n corresponds to n Service Opportunities, and the valid values of n are 1 to 13.
RW 0xB
8 BARB_BURST_ENABLE 
LSP BARB Burst Support
  
  This bit is valid only in DRD or host mode when using LSP EHST (((DWC_USB31_MODE == 2) || (DWC_USB31_MODE == 1)) && (DWC_USB31_CURRENT_GEN_HST_LSP == 2)).
   - 1'b1: The lbc interface between LSP and BMU supports burst transactions.
   - 1'b0: The lbc interface between LSP and BMU does not support burst transactions.
 RW 0x0
7 INTR_EP_PING_ENABLE 
Interrupt EP PING Support
   - 1'b1: Host sends PING for SS/SSP interrupt EPs.
   - 1'b0: Host does not send PING for SS/SSP interrupt EPs.
 RW 0x0
6:0 PERIODIC_UF_THR_FSLS 
Periodic microseconds threshold 
  
  Indicates the number of microseconds before the end of the microframe that the LSP cannot issue periodic requests to the PTL.  
  
  A value of n corresponds to n microseconds, which is (125-n)/125% approximately.
  
  For example, if you need a threshold of approximately 10% of one uframe, then program this field as 0.1*125us~=12us.
RW 0xC