GSBUSCFG0 

         Global SoC Bus Configuration Register 0
  
  This register configures system bus DMA options for the master bus, which may be configured as AHB, AXI, or Native. Options include burst length and cache type (bufferable/posted, cacheable/snoop, and so on). The application can program this register upon power-on, or a change in mode of operation after the DMA engine is halted.
  
  xHCI Register Power-On Value:
  
  If you are using a standard xHCI host driver, make sure to set the register's power-on value during coreConsultant configuration (DWC_USB31_GSBUSCFG0_INIT parameter) because the standard xHCI driver does not access this register.
  
  For more details on this register, refer to the following sections:
   - <link:ext>07_Registers_additional_info.fm:gsbuscfg0_usage,"Usage of Global SoC Bus Configuration Register 0 (GSBUSCFG0)"</link> section in the <link:ext>DWC_usb31_programming:Title,Programming Guide</link>
   - <link:ext>DWC_usb31_databook:sys_bus_int,"System Bus Interface"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C100

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATRDREQINFO

RW 0x0

DESRDREQINFO

RW 0x0

DATWRREQINFO

RW 0x0

DESWRREQINFO

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15_12

RW 0x0

DATBIGEND

RW 0x0

DESBIGEND

RW 0x0

reserved_9_8

RW 0x0

INCR256BRSTENA

RW 0x0

INCR128BRSTENA

RW 0x0

INCR64BRSTENA

RW 0x0

INCR32BRSTENA

RW 0x0

INCR16BRSTENA

RW 0x0

INCR8BRSTENA

RW 0x0

INCR4BRSTENA

RW 0x0

INCRBRSTENA

RW 0x1

GSBUSCFG0 Fields

Bit Name Description Access Reset
31:28 DATRDREQINFO 
DATRDREQINFO  
  
  AHB-prot/AXI-cache/OCP-ReqInfo for Data Read (DatRdReqInfo) 
  
  Input to BUS-GM.
 RW 0x0
27:24 DESRDREQINFO 
DESRDREQINFO
  
  AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read (DesRdReqInfo).
  
  Input to BUS-GM.
 RW 0x0
23:20 DATWRREQINFO 
DATWRREQINFO
  
  AHB-prot/AXI-cache/OCP-ReqInfo for Data Write (DatWrReqInfo).  
  
  Input to BUS-GM.
 RW 0x0
19:16 DESWRREQINFO 
DESWRREQINFO
  
  AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write (DesWrReqInfo) 
  
  Input to BUS-GM.
 RW 0x0
15:12 reserved_15_12 
Reserved_15_12
 RW 0x0
11 DATBIGEND 
Data Access is Big Endian
  
   This bit controls the endian mode for data accesses.
   - Little-endian 
   - Big-endian
  In big-endian mode, DMA access (both read and write) for packet data a Byte Invariant Big-Endian mode (see <link:ext>DWC_usb31_user:little_end_big_end,"Little-Endian and Big-Endian"</link> section in the <link:ext>DWC_usb31_user:Title,User Guide</link>).
  
  Note: Since AXI requires byte invariant endianness, setting DescBigend and DatBigEnd to one causes an address invariant transform to be applied, which is not appropriate. See section 9.3 and 9.4 of the AMBA AXI Specification. Hence for an AXI master (DWC_USB31_MBUS_TYPE=1), this bit must be set to zero.
RW 0x0
10 DESBIGEND 
Descriptor Access is Big Endian
  
  This bit controls the endian mode for descriptor accesses.
   - Little-endian
   - Big-endian 
  In big-endian mode, DMA access (both read and write) for descriptors uses a Byte Invariant Big-Endian mode (see <link:ext>DWC_usb31_user:little_end_big_end,"Little-Endian and Big-Endian"</link> section in the <link:ext>DWC_usb31_user:Title,User Guide</link>. 
  
  Data is considered as 'embedded data' in the descriptors in the following cases: 
   - Device mode: The buffer pointer of a Setup TRB points to the Setup TRB itself.
   - Host mode: The Immediate Data (IDT) bit in a Transfer TRB is set to 1.
  In device mode, if the system uses different endian modes for descriptor and data, software must not use 'embedded' data.
  
  In host mode, if the system uses different endian modes for data and descriptors, the controller treats 'embedded data' as descriptor (not as data) in terms of endian mode handling. If this is not the expectation of the system, the software must manipulate the 'embedded data' accordingly.
  
  Note: Since AXI requires byte invariant endianness, setting DescBigend and DatBigEnd to one causes an address invariant transform to be applied, which is not appropriate. See section 9.3 and 9.4 of the AMBA AXI Specification. Hence for an AXI master (DWC_USB31_MBUS_TYPE=1), this bit must be set to zero.
RW 0x0
9:8 reserved_9_8 
Reserved_9_8
 RW 0x0
7 INCR256BRSTENA 
INCR256 Burst Type Enable
  
  Input to BUS-GM. 
  
  For the AXI configuration, if software set this bit to 1, the AXI master uses INCR to do the 256-beat burst.
 RW 0x0
6 INCR128BRSTENA 
INCR128 Burst Type Enable
  
  Input to BUS-GM;
  
  For the AXI configuration, if software set this bit to 1, the AXI master uses INCR to do the 128-beat burst.
 RW 0x0
5 INCR64BRSTENA 
INCR64 Burst Type Enable
   - Input to BUS-GM; 
  For the AXI configuration, if software set this bit to 1, the AXI master uses INCR to do the 64-beat burst.
 RW 0x0
4 INCR32BRSTENA 
INCR32 Burst Type Enable
  
  Input to BUS-GM;
  For the AXI configuration, if software set this bit to 1, the AXI master uses INCR to do the 32-beat burst.
 RW 0x0
3 INCR16BRSTENA 
INCR16 Burst Type Enable
  
  Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to '1', the AHB/AXI master uses INCR to do the 16-beat burst.
 RW 0x0
2 INCR8BRSTENA 
INCR8 Burst Type Enable
  
  Input to BUS-GM; For the AHB/AXI configuration, if software set this bit to "1", the AHB/AXI master uses INCR to do the 8-beat burst.
 RW 0x0
1 INCR4BRSTENA 
INCR4 Burst Type Enable
  
  Input to BUS-GM; For the AXI configuration, when this bit is enabled the controller is allowed to do bursts of beat length 1, 2 and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and writes from being broken up into separate transfers.
 RW 0x0
0 INCRBRSTENA 
Undefined Length INCR Burst Type Enable (INCRBrstEna)
  
  Input to BUS-GM; This bit determines the set of burst lengths the master interface uses. It works in conjunction with the GSBUSCFG0[7:1] enables (INCR256/128/64/32/16/8/4).
  
  0: INCRX burst mode
  
  HBURST (for AHB configurations) and ARLEN/AWLEN (for AXI configurations) do not use INCR, except in case of non-aligned burst transfers. In the case of address-aligned transfers, they use only the following burst lengths:
   - 1
   - 2, 4 (if GSBUSCFG0.INCR4BrstEna = 1)
   - 8 (if GSBUSCFG0.INCR8BrstEna = 1)
   - 16 (if GSBUSCFG0.INCR16BrstEna = 1)
   - 32 (if GSBUSCFG0.INCR32BrstEna = 1)
   - 64 (if GSBUSCFG0.INCR64BrstEna = 1)
   - 128 (if GSBUSCFG0.INCR128BrstEna = 1)
   - 256 (if GSBUSCFG0.INCR256BrstEna = 1)
  Note: In case of non-address-aligned transfers, INCR may get generated at the beginning and end of the transfers to align the address boundaries, even though INCR is disabled.
  
  1: INCR (undefined length) burst mode
   - AHB configurations: HBURST uses SINGLE or INCR of any length less than or equal to the largest-enabled burst length of INCR4/8/16.
   - AXI configurations: ARLEN/AWLEN uses any length less than or equal to the largest-enabled burst length of INCR32/64/128/256.
  For cache line-aligned applications, this bit is typically set to 0 to ensure that the master interface uses only power-of-2 burst lengths (as enabled via GSBUSCFG0[7:0]).
RW 0x1