GCTL

Power Down Scale 
  
  The USB31 core_suspend_clk input replaces core_pipe_pclk as a clock source to a small part of the DWC_usb31 controller that operates when the ESS PHY is in its lowest power (P3) state, and therefore does not provide a clock.
  
  The Power Down Scale field specifies how many core_suspend_clk periods fit into a 16 kHz clock period. When performing the division, round up the remainder.
  
  For example, when using an 8-bit/16-bit/32-bit PHY and 25-MHz Suspend clock,
  
  Power Down Scale = 25000 kHz/16 kHz = 13'd1563 (rounder up)
  
  The LTSSM uses Suspend clock for 12-ms and 100-ms timers during suspend mode. According to the USB 3.1 specification, the accuracy on these timers is 0% to +50%.
   - 12 ms + 0~+50% accuracy = 18 ms (Range is 12 ms - 18 ms)
   - 100 ms + 0~+50% accuracy = 150 ms (Range is 100 ms - 150 ms).
  
  The suspend clock accuracy requirement is:
   - (12,000/62.5) * (GCTL[31:19]) * actual Suspend clock period must be between 12,000 and 18,000
   - (100,0000/62.5) * (GCTL[31:19]) * actual Suspend clock period must be between 100,000 and 150,000
  For example, if core_suspend_clk frequency varies from 7.5 MHz to 10.5MHz, then the value needs to programmed is:
  
  Power Down Scale = 10500/16 = 657 (rounded up; and fastest frequency used).
  
  Same requirement is applicable to suspend_clk
  
  Notes:
  
  When Hibernation is enabled,
   - This input is a minimum 32-kHz, maximum 200-kHz clock that is provided to the PMU and the controller. In the PMU, it is used to filter out glitches from the PHY, to time PIPE3 receiver detection, and to set PORTSC bits while in hibernation. In the controller, it is used to allow the sticky state to be restored before the bus_clk, USB 2.0 PHY clock, and USB 3.1 PHY clock are available.
   - The suspend clock must be always running .
   - When PMU filters are enabled (DWC_USB31_EN_PMU_FILTER=1), the maximum suspend_clk frequency is only 200 kHz because the suspend_clk is used to filter glitches from the PHY interfaces. A pulse is considered to be a glitch if it is less than 2.5us long (derived from USB 2.0). Therefore, sampling a signal on two consecutive rising edges of a 200-kHz clock guarantees that the signal is stable for more than 2.5us.
   - When PMU filters are disabled (DWC_USB31_EN_PMU_FILTER=0), the suspend_clk frequency may be faster (up to 30 MHz).

Master Filter Bypass
  
  When this bit is set to 1'b1, irrespective of the parameter `DWC_USB31_EN_BUS_FILTERS chosen, all the filters in the DWC_usb31_filter module (utmiotg_iddig, utmiotg_sessend, utmisrp_bvalid, utmiotg_vbusvalid & pipe_PowerPresent) are bypassed.  
  
  The double synchronizers to mac_clk preceding the filters are also bypassed. For enabling the filters, this bit must be 1'b0.

Bypass SetAddress in Device Mode
  
  This bit for simulation purposes only. In the actual hardware, this bit must be set to 1'b0. 
  
  When BYPSSETADDR bit is set, the device controller uses the value in the DCFG[DevAddr] bits directly for comparing the device address in the tokens. 
  
  For simulation, you can use this feature to avoid sending an actual SET ADDRESS control transfer on the USB, and make the device controller respond to a new address.
  
  When the xHCI Debug capability is enabled and this bit is set, the Debug Target immediately enters the configured state without requiring the Debug Host to send a SetAddress or SetConfig request.

U2RSTECN
  
  If the enhanced super speed connection fails during POLL or LMP exchange, the device connects at non-ESS mode. 
  
  On USB 2.0 reset device attempts three more times to connect at ESS, even if it previously failed to operate in ESS mode.
  This bit controls whether to attempt rx.detect eight times VS one time. Device controller on USB 2.0 reset checks for receiver termination eight times if this bit is set to zero, or only once if the bit is set to one
  
  Note: This bit is applicable only in device mode.

FRMSCLDWN
  
  This field scales down device view of a SOF/USOF/ITP duration.
  
  For ESS/HS mode:
   - Value of 2'h3 implements interval to be 15.625 us
   - Value of 2'h2 implements interval to be 31.25 us
   - Value of 2'h1 implements interval to be 62.5 us
   - Value of 2'h0 implements interval to be 125us
  For FS mode, the scale-down value is multiplied by 8.
  
  When xHCI Debug Capability is enabled, this field also scales down the MaxPacketSize of the IN and OUT bulk endpoint to allow more traffic during simulation. It can only be changed from a non-zero value during simulation. 
   - 2'h0: 1024 bytes
   - 2'h1: 512 bytes
   - 2'h2: 256 bytes
   - 2'h3: 128 bytes

PRTCAPDIR: Port Capability Direction 
   - 2'b01: for Host configurations
   - 2'b10: for Device configurations
   - 2'b00, 2'b11: not supported
  Note: For static Host-only/Device-only applications, use DRD Host or DRD Device mode.
  
  The sequence for switching modes in DRD configuration is as follows: 
  
  Switching from Device to Host:
  
   If a standard xHCI driver is used and if configuration is DRD, then boot code should do the following prior to loading the xHCI driver
  
  1. Set GCTL[13:12] (PrtCapDir) to 2'b01 (Host mode).
  
  2. Reset the host using USBCMD.HCRST.
  
  3. Follow the steps in <link:ext>10_Host_Prog_Model.fm:init_host_regs,"Initializing Host Registers"</link> section.
  
  Switching from Host to Device:
  
  1. Set GCTL[13:12] (PrtCapDir) to 2'b10 (Device mode).
  
  2. Reset the device by setting DCTL[30] (CSftRst).
  
  3. Follow the steps in <link:ext>09_Dev_Prog_Model.fm:init_dev_regs,"Initializing Registers"</link> section.
  
  Programming this field with random data causes the controller to keep toggling between the host mode and the device mode.
  
  If the configured value is set to host mode, VBUS is driven immediately after power-on reset. If the end user plugs in the core into a PC and the application configures the controller as a device later, the VBUS will be driven from both sides of the cable. This will potentially damage the PC host.
  

Core Soft Reset 
   - 1'b0 - No soft reset
   - 1'b1 - Soft reset to core
  Clears the interrupts and all the CSRs except the following registers:
   - GCTL
   - GUCTL
   - GSTS
   - USB31_IP_NAME
   - GGPIO
   - GUID
   - GUSB2PHYCFGn registers
   - GUSB3PIPECTLn registers
   - DCFG
   - DCTL
   - DEVTEN
   - DSTS
  When you reset PHYs (using GUSB3PHYCFG or GUSB3PIPECTL registers), you must keep the controller in reset state until PHY clocks are stable. This controls the bus, RAM, and MAC domain resets. For details, refer to the <link:ext>DWC_usb31_databook:reset_gen,"Reset Generation"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>.
  
  Note: Programming this field with random data will reset the internal logic of the host controller.

Reserved

Disable U1/U2 timer Scaledown  
  
  If set to '1' along with GCTL[5:4] (ScaleDown) = 2'b11, disables the scale down of U1/U2 inactive timer values. This is for simulation mode only.

Debug Attach
  
  When this bit is set, 
   - ESS Link proceeds directly to the Polling link state (after RUN/STOP in the DCTL register is asserted) without checking remote termination; 
   - Link LFPS polling timeout is infinite;
   - Polling timeout during TS1 is infinite (in case link is waiting for TXEQ to finish).
  This register is applicable only in device mode.

RAM Clock Select 
  
  The ram_clk_out must be connected back to ram_clk_in for this feature to work. This register field setting can be changed only in device mode.
   - 2'b00: bus clock
   - 2'b01: pipe clock 
   - 2'b10: In device mode, pipe/2 clock.
   - 2'b11: In device mode, selects mac2_clk as ram_clk when 8-bit UTMI or ULPI is used. (Not supported in 16-bit UTMI mode)
  In device mode, upon a USB reset and USB disconnect, the hardware clears these bits to 2'b00.  
  
  Note:
   - In device mode, if you set RAMClkSel to 2'b11 (mac2_clk), the controller internally switches the ram_clk to bus_clk when the link state changes to Suspend (L2 or L3), and switches the ram_clk back to mac2_clk when the link state changes to resume or U2.
   - In host mode, this register field setting should not be modified. 
  A value of 2 can be chosen only if the pipe data width is 8 or 16 bits. In this case the when the ram_clk is switched to pipe_clk, it uses pipe_clk/2 instead of pipe_clk. If a value of 3 is chosen for RAMClkSel, then when ram_clk is switched to pipe_clk, then pipe_clk is used without any divider. 
   - In device mode, when RAMClkSel != 2'b00, the bus_clk_early frequency can be a minimum of 1 MHz. This is tested in simulation and also in hardware with Linux, Microsoft Windows 8, and MCCI Windows7 host drivers. Only control and non periodic transfers are supported when bus_clk is 1 MHz. For periodic applications, the bus_clk_early minimum frequency is higher depending on your application and SoC bus. Even though 1 MHz has been tested with standard host drivers, Synopsys recommends 5 MHz minimum for ASIC designs to provide a margin or at least have a backup option to increase the bus_clk frequency to 5 MHz if needed.

Scale-Down Mode 
  
  When Scale-Down mode is enabled for simulation, the controller uses scaled-down timing values, resulting in faster simulations.
  
  When Scale-Down mode is disabled, actual timing values are used. This is required for hardware operation.
  
  HS/FS/LS Modes
   - 2'b00: Disables all scale-downs. Actual timing values are used.
   - 2'b01: Reserved
   - 2'b10: Reserved
   - 2'b11: Enables scale-down of all timing values of USB events. These include Speed enumeration, HNP/SRP, and suspend and resume.
  ESS Mode
   - 2'b00: Disables all scale-downs. Actual timing values are used.
   - 2'b01: Enables scaled down SS timing and repeat values including:
   -- (1) Number of TxEq training sequences reduce to 8;
   -- (2) LFPS polling burst time reduce to 256 nS;
   -- (3) LFPS warm reset receive reduce to 30 uS. 
  Refer to the rtl_vip_scaledown_mapping.xls file under <workspace>/sim/SoC_sim directory for the complete list.
   - 2'b10: No TxEq training sequences are sent. Overrides Bit 4.
   - 2'b11: Enables bit 0 and bit 1 scale-down timing values.

Disable Scrambling 
  
   Request to disable scrambling to Link Partner on next transition to Recovery or Polling.

U2EXIT_LFPS
  
  If this bit is,
   - 0: the link treats 248ns LFPS as a valid U2 exit. 
   - 1: the link waits for 8us of LFPS before it detects a valid U2 exit. 
  This bit is added to improve interoperability with a third party host controller. This host controller in U2 state while performing receiver detection generates an LFPS glitch of about 4us duration. This causes the device to exit from U2 state because the LFPS filter value is 248ns. With the new functionality enabled, the device can stay in U2 while ignoring this glitch from the host controller.

GblHibernationEn
  
  This bit enables hibernation. If hibernation is not enabled through this bit, the PMU immediately accepts the D0->D3 and D3->D0 power state change requests, but does not save or restore any controller state.
  
  In addition, the PMUs never drive the PHY interfaces and let the controller continue to drive the PHY interfaces.
  
   - Note: This field is only read-write when hibernation is enabled i.e. [DWC_USB31_EN_PWROPT==2] else its read-only

Disable Clock Gating 
  
  If this bit is set to 1, internal clock gating is disabled