GHWPARAMS4 

         Global Hardware Parameters Register 4
  
  This register contains the hardware configuration options that you can select in the coreConsultant GUI.  
  
  Note: 
   - For a description of each parameter, refer to the "Parameter Descriptions" chapter in the <link:ext>DWC_usb31_databook:Title,Databook</link>. This information is also available in coreConsultant by right-clicking the parameter label and selecting "What's This" or by clicking the Help tab.  
   - Some of the global hardware parameters are not currently modifiable in coreConsultant. These settings are in the  <workspace>/src/${ldsg}_params.svh file; you must not change them.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C150

Size: 32

Offset: 0x50

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ghwparams4_31_28

RO 0x4

ghwparams4_27_23

RO 0x10

ghwparams4_22

RO 0x1

ghwparams4_21

RO 0x0

ghwparams4_20_17

RO 0x1

ghwparams4_16_13

RO 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ghwparams4_16_13

RO 0x1

ghwparams4_12_6

RO 0x0

ghwparams4_5_0

RO 0x10

GHWPARAMS4 Fields

Bit Name Description Access Reset
31:28 ghwparams4_31_28 
`DWC_USB31_BMU_LSP_DEPTH
 RO 0x4
27:23 ghwparams4_27_23 
`DWC_USB31_BMU_PTL_DEPTH
 RO 0x10
22 ghwparams4_22 
`DWC_USB31_EN_ISOC_SUPT
 RO 0x1
21 ghwparams4_21 
`DWC_USB31_EXT_BUFF_CONTROL
 RO 0x0
20:17 ghwparams4_20_17 
`DWC_USB31_NUM_ESS_USB_INSTANCES
 RO 0x1
16:13 ghwparams4_16_13 
`DWC_USB31_HIBER_SCRATCHBUFS
  
  This field is the number of external scratchpad buffers the controller requires to save its internal state in device mode. Each buffer is assumed to be 4KB. The scratchpad buffer array must have this many buffer pointers.
 RO 0x1
12:6 ghwparams4_12_6 
Reserved
 RO 0x0
5:0 ghwparams4_5_0 
`DWC_USB31_CACHE_TRBS_PER_TRANSFER
 RO 0x10