GUCTL2 

         Global User Control Register 2
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C608

Size: 32

Offset: 0x508

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PERIODIC_UF_THR

RW 0xC

ASYNC_UF_THR

RW 0x1

PERIODIC_TXDMA_UF_THR

RW 0x8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PERIODIC_TXDMA_UF_THR

RW 0x8

SVC_OPP_PER_SSP

RW 0x1

SVC_OPP_PER_SS

RW 0x0

SVC_OPP_PER_HS

RW 0x2

SVC_OPP_PER_FSLS

RW 0x0

MAX_REISU_CNT

RW 0x3

SCHEDDULE_LT_THR

RW 0x0

GUCTL2 Fields

Bit Name Description Access Reset
31:25 PERIODIC_UF_THR 
Periodic microseconds threshold 
  
  Indicates the number of microseconds before the end of the microframe that the LSP stops issuing periodic requests to the PTL.  
  
  A value of n corresponds to n microseconds, which is (125-n)/125% approximately.
  
  For example, if you need a threshold of approximately 10% of one uframe, then program this field as 0.1*125us~=12us.
RW 0xC
24:18 ASYNC_UF_THR 
Asynchronous microseconds threshold 
  
  Indicates the number of microseconds before the end of the microframe that the LSP stops issuing asynchronous requests to the PTL.
  
  A value of n corresponds to n microseconds, which is (125-n)/125% approximately.
  
  For example, if you need a threshold of approximately 2% of one uframe, then program this field as 0.02*125us~=2us.
RW 0x1
17:11 PERIODIC_TXDMA_UF_THR 
  Indicates the number of microseconds before the end of the microframe that the LSP needs to start issuing TX DMA for periodic OUT endpoints scheduled in the next microframe.
  
  A value of n corresponds to n microseconds, which is (125-n)/125% approximately.
  
  For example, if you need a threshold of approximately 32% of one uframe, then program this field as 0.32*125us~=40us.
RW 0x8
10:9 SVC_OPP_PER_SSP 
Service opportunities to Enhanced SuperSpeedPlus bulk endpoints
  
  Indicates the number of Service Opportunities (SOs) that will be allocated to Enhanced SuperSpeedPlus bulk endpoints.
  
  The encoding used is as follows:
   - 0: maxburstsize service opportunities
   - 1: 2* maxburstsize service opportunities
   - 2: 4*maxburstsize service opportunities
   - 3: maxburstsize/2 service opportunities
  where, Maxburstsize is the maximum number of packets the endpoint can send/receive as part of the burst.
RW 0x1
8:7 SVC_OPP_PER_SS 
Service opportunities to SuperSpeed bulk endpoints
  
  Indicates the number of Service Opportunities (SOs) that will be allocated to SuperSpeed bulk endpoints.
  
  The encoding used is as follows:
   - 0: maxburstsize service opportunities
   - 1: 2* maxburstsize service opportunities
   - 2: 4*maxburstsize service opportunities
   - 3: maxburstsize/2 service opportunities
  where, Maxburstsize is the maximum number of packets the endpoint can send/receive as part of the burst.
RW 0x0
6:5 SVC_OPP_PER_HS 
Service opportunities to HS bulk endpoints
  
  Indicates the number of Service Opportunities (SOs) that will be allocated to HS bulk endpoints.
  
  The encoding used is as follows:
   - 0: 1 service opportunity
   - 1: 1 service opportunities
   - 2: 3 service opportunities
   - 3: 4 service opportunities
 RW 0x2
4:3 SVC_OPP_PER_FSLS 
Service opportunities to FS/LS bulk endpoints
  
  Indicates the number of Service Opportunities (SOs) that will be allocated to FS/LS bulk endpoints.
  
  The encoding used is as follows:
   - 0: 1 service opportunity
   - 1: 1 service opportunities
   - 2: 3 service opportunities
   - 3: 4 service opportunities
 RW 0x0
2:1 MAX_REISU_CNT 
Indicates the number of re-issue opportunities that will be allocated to OUT transactions that meet the following criteria:
   - Bulk EP types
   - Receives a link abort due to:
   -- Lack of credits   
   -- Link in U1, U2 or Recovery
   -- Not able to fit all the packets into the remainder of the microframe before the ITP
  Valid values are 0, 1, 2 or 3.
 RW 0x3
0 SCHEDDULE_LT_THR 
  Indicates that the Host LSP schedulers should schedule transactions before all the TRBs have been fetched. This may increase performance by allowing transactions to start earlier, but may also have a negative effect because more TRQ space will be used.
 RW 0x0