GBUSERRADDRLO

         Global SoC Bus Error Address Register - Low
  
  When the AHB or AXI Master Bus returns an "Error" response, the "SoC Bus Error" is generated. In the Host mode, the host_system_err port indicates this condition. In addition, it is also indicated in the USBSTS.HSE field. In the Device mode, the GSTS.BusErrAddrVld field is the only indication of the SoC Bus Error.
  
  Note for AXI configuration:
  
  Due to the nature of AXI, it is possible that multiple AXI transactions are active at a time. The DWC_usb31 controller does not keep track of the start address of all outstanding transactions. Instead, it keeps track of the start address of the DMA transfer associated with all active transactions. It is this address that is reported in the GBUSERRADDR when a bus error occurs.
  
  For example, if the DWC_usb31 controller initiates a DMA transfer to write 1k of packet data starting at buffer address 0xABCD0000, and this DMA is broken up into multiple 256B bursts on the AXI, then if a bus error occurs on any of these associated AXI transfers, the GBUSERRADDR reflects the DMA start address of 0xABCD0000 regardless of which AXI transaction received the error.


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100C100`	`0x1100C130`

Size: 32

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`BUSERRADDR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`BUSERRADDR` `RO 0x0`

GBUSERRADDRLO Fields

Bit Name Description Access Reset

31:0

Bit	Name	Description	Access	Reset
31:0	`BUSERRADDR`	Bus Address - Low (BusAddrLo) This register contains the lower 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note: Only supported in AHB and AXI configurations.	`RO`	`0x0`

BUSERRADDR

Bus Address - Low (BusAddrLo)
  This register contains the lower 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1.
  It can only be cleared by resetting the controller.
  
  Note: Only supported in AHB and AXI configurations.

RO

0x0