GSBUSCFG1 

         Global SoC Bus Configuration Register 1
  
  xHCI Register Power-On Value:
  
  If you are using a standard xHCI host driver, make sure to set the register's power-on value during coreConsultant configuration (DWC_USB31_GSBUSCFG1_INIT parameter) because the standard xHCI driver does not access this register.
  
  For more details on this register, refer to the following section:
   - <link:ext>DWC_usb31_databook:sys_bus_int,"System Bus Interface"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C104

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_17

RO 0x0

ExtdPipeTransLimit

RW 0x3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ExtdPipeTransLimit

RW 0x3

EN1KPAGE

RW 0x0

PipeTransLimit

RW 0xF

reserved_7_0

RW 0x0

GSBUSCFG1 Fields

Bit Name Description Access Reset
31:17 reserved_31_17 
Reserved
 RO 0x0
16:13 ExtdPipeTransLimit 
AXI Pipelined Transfers Extended Burst Request Limit
  
  The {ExtdPipeTransLimit, PipeTransLimit} fields controls the number of outstanding extended pipelined transfer requests the AXI master pushes to the AXI slave. 
  
  When the AXI master reaches this limit, it does not make any more requests on the AXI ARADDR and AWADDR buses until the associated data phases complete.
  
  This field is encoded as follows:
   - 'h0: 1 request
   - 'h1: 2 requests
   - 'h2: 3 requests
   - 'h3: 4 requests
   - and, so on
  Note: This field must be programmed to a value lesser than DWC_USB31_MAXI_REQUESTS.
 RW 0x3
12 EN1KPAGE 
1k Page Boundary Enable
   - When this bit is disabled, the AXI master (DMA data) breaks transfers at the 4k page boundary. 
   - When this bit is enabled, the AXI master (DMA data) breaks transfers at the 1k page boundary.
 RW 0x0
11:8 PipeTransLimit 
AXI Pipelined Transfers Burst Request Limit
  
  The {ExtdPipeTransLimit, PipeTransLimit} fields controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave. 
  
  When the AXI master reaches this limit, it does not make any more requests on the AXI ARADDR and AWADDR buses until the associated data phases complete.
  
  This field is encoded as follows:
   - 'h0: 1 request
   - 'h1: 2 requests
   - 'h2: 3 requests
   - 'h3: 4 requests
   - and, so on
  Note: This field must be programmed to a value lesser than DWC_USB31_MAXI_REQUESTS.
 RW 0xF
7:0 reserved_7_0 
Reserved_7_0
 RW 0x0