GFIFOPRIDBC 

         Global Host Debug Capability DMA Priority Register
  
  This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and TXFIFO DMA priority registers, when the DbC mode is enabled.
  
  Priority settings are specified in relation to the low-priority SS speed group:
   - 1. Normal priority indicates that the DbC FIFOs are considered identical to the Host SS low-priority FIFOs.
   - 2. Low priority indicates that the DbC FIFOs are considered to have lower priority than all Host SS FIFOs.
   - 3. High priority indicates that the DbC FIFOs are considered higher priority than the Host SS low-priority FIFOs but lower priority than the Host SS high-priority FIFOs.
  This register is present only when the controller is configured to operate in Host Debug Capability (DbC) mode.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C620

Size: 32

Offset: 0x520

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_31_2

RO 0x0

gfifopridbc

RW 0x0

GFIFOPRIDBC Fields

Bit Name Description Access Reset
31:2 reserved_31_2 
Reserved
 RO 0x0
1:0 gfifopridbc 
Host DbC DMA priority
 RW 0x0