GSTS
Global Status Register
Module Instance | Base Address | Register Address |
---|---|---|
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000
|
0x1100C100
|
0x1100C118
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Size: 32
Offset: 0x18
Access: RW
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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GSTS Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:20 |
CBELT
|
Current BELT Value In Host mode, this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command. |
RO
|
0x7E8
|
19:12 |
reserved_19_12
|
Reserved |
RO
|
0x0
|
11:8 |
reserved_11_8
|
Reserved |
RO
|
0x0
|
7 |
Host_IP
|
Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue. |
RO
|
0x0
|
6 |
Device_IP
|
Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue. |
RO
|
0x0
|
5 |
CSRTimeout
|
CSR Timeout When this bit is 1'b1, it indicates that the software performed a write or read to a controller register that could not be completed within the CSR access time. For more details, refer to the <link:ext>07_Registers_additional_info.fm:csr_timeout_mech,"CSR Timeout Mechanism"</link> section. |
RW
|
0x0
|
4 |
BUSERRADDRVLD
|
Bus Error Address Valid (BusErrAddrVld) Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error. Note: Only supported in AHB and AXI configurations. |
RW
|
0x0
|
3:2 |
reserved_3_2
|
Reserved |
RO
|
0x0
|
1:0 |
CURMOD
|
Current Mode of Operation (CurMod) Indicates the current mode of operation: - 2'b00: Device mode - 2'b01: Host mode |
RO
|
0x0
|