AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel Arria 10 FPGA Development Board

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AN-847 | 2020.12.21

Version Information

Updated for:
Intel® Quartus® Prime Design Suite 20.3

1. Introduction

The Intel^® Quartus^® Prime Pro Edition software supports verification of block-based design flows with the Signal Tap logic analyzer. This tutorial demonstrates how to incorporate internal signal verification into design block reuse flows in the Intel^® Quartus^® Prime Pro Edition software.

A design block is the logic comprising a hierarchical design instance. Block-based design flows enable preservation of blocks within a project via Incremental Block-Based Compilation, as well as reuse of design blocks in other projects via Design Block Reuse. To preserve or reuse a design block, you must designate the block as a design partition.

Figure 1. Core Partition Reuse Example

Verifying a block-based design requires planning to ensure visibility of logic inside partitions and communication with the Signal Tap logic analyzer. The preparation steps depend on whether you are reusing a core partition or a root partition.

For basic information about designing with reusable blocks, refer to the Intel^® Quartus^® Prime Pro Edition User Guide: Block-Based Design . For step-by-step instructions on reusing design blocks, refer to AN 839: Design Block Reuse Tutorial for Intel^® Arria^® 10 FPGA Development Board .

This tutorial uses a provided design example to walk through the steps required to perform Signal Tap debugging in reused design blocks.

1.1. Tutorial Software and Hardware

Steps in this tutorial correspond with the following Intel software and hardware:

Linux installation of Intel^® Quartus^® Prime Pro Edition software version 20.3, with Intel^® Arria^® 10 device support.
The Intel^® Arria^® 10 GX FPGA Development Kit.

You can adapt this tutorial for Windows and other software or hardware configurations.

1.2. Tutorial Files

This tutorial includes the following design example organized into directories that correspond with the flow (Core or Root partition reuse) and role (Developer or Consumer).

https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/a10-pcie-devkit-design-block-reuse-stp-v20-3.zip

Figure 2. Tutorial Directory Structure

The Completed directories contain the final versions of all files required to complete that tutorial module. You can use the files in Completed directories to bypass tutorial steps, or skip to the final step of the tutorial module. The Scripts directories contain bash scripts and files to restore the single project.

To restore all of the tutorial files to the original run the following from the project directory:
```
./restoreall.sh
```
To restore a single project, run the following from the Consumer or Developer directory:
```
Script/restore.sh
```

¹ This feature has some known limitations. Refer to Why I can't compile Intel Stratix 10 partitions exported from another project with a different top level and Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp.

1.3. Signal Tap with Core Partition Reuse

To perform verification in a reusable core partition, in the Developer project, you must identify the signals of interest, and then make those signals visible to a Signal Tap logic analyzer instance. The Intel^® Quartus^® Prime software supports two methods of making core partition signals visible for verification:

Signal Tap HDL instance—In the Developer project, you create a Signal Tap HDL instance in the reusable core partition and connect the signals of interest to that instance. The Compiler ensures top level visibility of Signal Tap instances inside partitions. Since the root partition and the core partition have separate HDL instances, the Signal Tap files are also separate.
The Consumer must generate one Signal Tap file for each HDL instance present in the design.
Partition boundary ports—In this method, the Developer directly assigns signals as ports to the partition boundary. The top level partition contains an instance of Signal Tap, and signals in the partition boundary connect to it. Assigning boundary ports simplifies the management of hierarchical blocks, by automatically creating ports and tunneling through layers of logic, without making RTL changes. You create partition boundary ports through an Intel^® Quartus^® Prime Settings File (.qsf) assignment, or with the Assignment Editor.
The Developer must include the user created partition boundary ports in the black box file. This action allows the Consumer to tap these ports as pre-synthesis or post-fit nodes.

Figure 3. Consumer Debug Setup with Reused Core Partition

The Consumer can add the Signal Tap logic analyzer to the parent partition with any of these methods:

Signal Tap HDL instance
Signal Tap GUI to tap pre-synthesis nodes
Signal Tap GUI to tap post-fit nodes

In this core partition reuse tutorial, the Developer creates partition boundary ports with the Assignment Editor, and the Consumer adds pre-synthesis nodes to the parent partition with the Signal Tap GUI. The following figure describes the Developer and Consumer flows:

Figure 4. Tutorial Design Flow for Core Partition Reuse

1.4. Signal Tap with Root Partition Reuse

In a root partition reuse flow, the Developer extends the debug fabric into the Reserved Core partition with a debug bridge. The debug bridge also allows debugging of the reserved core partition in the Consumer project. The components of a debug bridge are:

SLD JTAG Bridge Agent Intel^® FPGA IP : Instantiate in the higher-level partition to connect to an SLD JTAG Bridge Host in the child partition.
SLD JTAG Bridge Host Intel^® FPGA IP : Instantiate in the child partition to connect to an SLD JTAG Bridge Agent in the higher-level partition.

With the bridge in place, the Developer adds the Signal Tap logic analyzer to the root partition with either of the following methods:

Signal Tap HDL instance
Signal Tap GUI to tap pre-synthesis or post-fit nodes

The Intel^® Quartus^® Prime Pro Edition software supports multiple instances of bridge components in partitions and their children. The Compiler assigns an index number to distinguish each instance. The bridge index for the root partition is always None. You can view the bridge index for child partitions in the synthesis report, under JTAG Bridge Agent Instance Information.

Each instance of the Signal Tap logic analyzer can only connect within the partition that the instance resides. Therefore, the root partition and reserved core partition require separate Signal Tap files in this flow.

The Consumer must instantiate the SLD JTAG Bridge Host in the reserved core partition, and add Signal Tap to the reserved core partition with either of the following methods:

Signal Tap HDL instance
Signal Tap GUI to tap pre-synthesis or post-fit nodes

Figure 5. Debug Setup with Reused Root Partition

In this root partition reuse tutorial, the Developer adds an HDL instance of the Signal Tap logic analyzer to debug the root partition, and adds bridge components to enable debug of the reserved core partition. Then, in the Consumer project, the Consumer adds the SLD JTAG Bridge Host to enable debug of the reserved core partition, and uses the Signal Tap GUI to tap pre-synthesis nodes.

Figure 6. Tutorial Design Flow for Root Partition Reuse

2. Core Partition Reuse Debug—Developer

Process Description

In this tutorial module, the Developer assigns signals as ports to the partition boundary using the Assignment Editor, and then exports the core partition to a .qdb file. As a result, these user created boundary ports are available for debug as pre-synthesis nodes in the Consumer project, as a part of the reused .qdb file.

Completed Tutorial Files

In the a10_pcie_devkit_design_block_reuse_stp folder, the Core_Partition_Reuse/Completed/Developer/ directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Step 1: Creating a Core Partition
Step 2: Creating Partition Boundary Ports
Step 3: Compiling and Checking Debug Nodes
Step 4: Exporting the Core Partition and Creating the Black Box File
Step 5: Copying Files to Consumer Project
Step 6: Creating a Signal Tap File (Optional)
Step 7: Programming the Device and Verifying the Hardware
Step 8: Verifying Hardware with Signal Tap

2.1. Step 1: Creating a Core Partition

During this step, you open the project, run synthesis, and define a design partition for the core logic.

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project, and open the a10_pcie_devkit_design_block_reuse_stp/Core_Partition_Reuse/Developer/top.qpf project file.
On the Compilation Dashboard, click Analysis & Synthesis to synthesize the design. When synthesis is complete, the Compilation Dashboard displays a check mark.

Figure 7. Compilation Dashboard
In the Project Navigator, right-click the u_blinking_led_top instance in the Hierarchy tab, and then click Design Partition > Default. A design partition icon appears next to each instance you assign.

Figure 8. Create Design Partition

Note: If the Design Partition Window is not visible on the GUI, click Assignments > Design Partitions Window.

2.2. Step 2: Creating Partition Boundary Ports

Follow these steps to create partition boundary ports to expose signals from the parent partition.

In the Intel^® Quartus^® Prime software, click Assignments > Assignment Editor.
In the Assignment Editor, locate the <<new>> row at the bottom of the list.
Double-click the To column, and then click the Node Finder button.

Figure 9. Assignment Editor
In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.

Figure 10. Node Finder Search

The Matching Nodes list shows signals that match the search criteria.
In the Matching Nodes list, expand u_blinking_led_top > u_counter > count_int.
Select count_int[0], count_int[1], count_int[2], and count_int[24], and click > to move them to the Nodes Found list. Do not click OK.
In the Matching Nodes list, expand u_blinking_led_top, and select value. Click >.

Figure 11. Node Finder Copy Nodes
Click OK to close the Node Finder.
In the Assignment Editor window, for each of these nodes, populate information for rest of the columns.
For example, for node u_blinking_led_top|u_blinking_led|value, double-click Assignment Name and select Create Partition Boundary Ports. Double-click value to provide a port name db_value. Leave rest of the columns as default.
Figure 12. Assignment Editor
Click File > Save to save all changes.

Optionally, you can verify the following assignments in /Core_Partition_Reuse/Developer/top.qsf.

set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_1 \
-to u_blinking_led_top|u_counter|count_int[1]
set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_24 \
-to u_blinking_led_top|u_counter|count_int[24]
set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_2 \
-to u_blinking_led_top|u_counter|count_int[2]
set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_value \
-to u_blinking_led_top|value
set_instance_assignment -name CREATE_PARTITION_BOUNDARY_PORTS db_count_0 \
-to u_blinking_led_top|u_counter|count_int[0]

2.3. Step 3: Compiling and Checking Debug Nodes

Click Compile Design on the Compilation Dashboard.

Figure 13. Full Compilation in Compilation Dashboard
Open the compilation report by clicking Processing > Compilation Report.
Under Table of Contents, find Synthesis > In-System Debugging > Create Partition Boundary Ports.

Figure 14. Create Partition Boundary Ports

2.4. Step 4: Exporting the Core Partition and Creating the Black Box File

After compilation, you export the core partition and create a supporting black box port definitions file. This tutorial reuses the final compilation snapshot.

Click Project > Export Design Partition. Select blinking_led_top for the Partition name, and the final Snapshot for export.
Confirm blinking_led_top.qdb as the Partition Database File name, and then click OK. The final blinking_led.qdb that you export preserves the placement and routing information from the Developer project reused in the Consumer project.
To create the black box file, click File > New, select SystemVerilog HDL File under Design Files, and then click OK.
A blank .sv file opens to allow you to enter the port definitions for the partition you export and the partition boundary ports created in Step 3: Compiling and Checking Debug Nodes.

Include any Verilog parameters or VHDL generics in the definition. The port definitions in the black box file must look just like the original, without the logic RTL.

module blinking_led_top(
	output [3:0] value,
	input clock,
	output db_count_0,
	output db_count_1,
	output db_count_2,
	output db_count_24,
	output db_value_0,
	output db_value_1,
	output db_value_2,
	output db_value_3
	);

endmodule

Save the black box file as blinking_led_top_bb.sv. When saving this file, turn off the option to Add file to current project.

2.5. Step 5: Copying Files to Consumer Project

After exporting the core partition and creating the black box file, copy the files to the Consumer project directory for subsequent use.

Copy the blinking_led_top.qdb and blinking_led_top_bb.sv files to the Core_Partition_Reuse/Consumer/ directory.

Note: The .sdc file does not influence the logic, placement, or routing of a finalized partition in the Consumer project.

In the Core Partition Reuse Debug-Consumer tutorial module, the Consumer integrates the blinking_led_top.qdb and blinking_led_top_bb.sv files into the Consumer project.

2.6. Step 6: Creating a Signal Tap File (Optional)

In this step, you configure the Signal Tap logic analyzer, and then tap partition boundary ports and pre-synthesis nodes from the parent partition to debug in the Developer project. Configuring the Signal Tap logic analyzer includes adding a reference clock and specifying acquisition settings.

In the Intel^® Quartus^® Prime Pro Edition software, click Tools > Signal Tap Logic Analyzer.

Figure 15. Signal Tap Logic Analyzer Window
In the Instance Manager, click auto_signaltap_0.
In the Setup tab, double-click to launch the Node Finder.
In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.
In the Matching Nodes list, expand u_blinking_led_top. Select db_value_0, db_value_1, db_value_2, and db_value_3.

Figure 16. Node Finder Copy Nodes
In the Matching Nodes list, expand the u_blinking_led_top > u_counter > count_int.
From the node list, select count_int[0], count_int[1], count_int[2], and count_int[24], and insert the nodes by clicking >.
Click Insert, and then Close.
In the Signal Tap window, under Signal Configuration, click (…) next to the Clock field.
In the Node Finder, search for *, and select the clock.
Click >, and then click OK to close.

Figure 17. Clock Signal in Node Finder
Leave all other options as default under Signal Configuration.
Go to File > Save and save the file as stp_core_partition_reuse.stp.
A dialog box appears asking if you want to enable Signal Tap file for the project.
Click Yes, and close the file.
Click Compile Design on the Compilation Dashboard.

2.7. Step 7: Programming the Device and Verifying the Hardware

To open the Intel^® Quartus^® Prime Programmer, click Tools > Programmer.
Connect the board cables:
- JTAG USB cable to board
- Power cable attached to board and power source
Turn on power to the board.
In the Intel^® Quartus^® Prime Programmer, click Hardware Setup.

Figure 18. Hardware Setup
In the Hardware list, select USB-BlasterII, and then click Close. The device chain appears.

Note: If the device chain does not appear, verify the board connections.
Click Auto-Detect. The device chain populates.
In the Found Devices list, select the device that matches your design and click OK. For this tutorial, select the 10AX115S2 device that matches the 10AX115S2F45I1SG FPGA on the Intel^® Arria^® 10 GX Development Kit.

Figure 19. Select Device
Right-click the 10AX115S2 row in the file list, and then click Change File.

Figure 20. Programmer Window
Browse to select the top.sof file from the appropriate tutorial/output_files/ directory.
Enable the Program/Configure option for the 10AX115S2 row.

Figure 21. Program/Configure Option
Click Start. The progress bar reaches 100% when device configuration is complete. The device is now fully configured and in operation.

Figure 22. Programming Successful

Note: If device configuration fails, make sure the device you select for configuration matches the device you specify during .sof file generation.
Verify the LEDs behavior.

After completing this tutorial module:

LEDs AC6 and AE6 map to blinking_led_top.
LEDs AC7 and AF6 map to top-level design.

The blinking_led_top core flashes LEDs in binary order, and the top-level design does not illuminate any LEDs.

2.8. Step 8: Verifying Hardware with Signal Tap

In the Signal Tap window, click File > Open, and open stp_core_partition_reuse.stp.
Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
In the JTAG Chain Configuration tab, set up the JTAG connection to the board by clicking Setup and then selecting the USB-BlasterII under Hardware.

The device populates automatically.

Figure 23. JTAG Scan Configuration

The Instance Manager window shows Ready to acquire.
Figure 24. Instance Manager
To set the trigger condition, select count_int[24], right-click the column under Trigger Conditions, and set to Falling Edge.

Figure 25. Trigger Conditions
Run analysis by clicking Processing > Run Analysis.
When the analysis finishes, the Waveform tab shows the captured data.

Figure 26. Waveform after Signal Tap Analysis

The count_int[27:24] register in u_blinking_led_top|u_counter|count_int[27:24] drives u_blinking_led_top|u_blinking_led|value[3:0].
The partition boundary ports created for each bit of value[3:0] are db_value_3, db_value_2, db_value_1, and db_value_0.
The value of db_value_0 changes a cycle later after count_int[24] transitions to 0. The count_int[2:0] shows the transitioning of the counter during this process

3. Core Partition Reuse Debug—Consumer

In this tutorial, the Consumer receives a final core partition with boundary ports that correspond to signals useful for debugging. The Consumer adds the black box file and assigns the .qdb in the Consumer project. Then, the Consumer debugs the parent and reused core partition with a Signal Tap HDL instance, tapping partition boundary ports as pre-synthesis nodes.

Because the exported .qdb includes compiled netlist information, the Consumer project must target the same FPGA device part number, and use the same Intel^® Quartus^® Prime version as the Developer project.

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Step 1: Adding Files and Running Synthesis
Step 2: Creating a Signal Tap File
Step 3: Creating a Partition for blinking_led_top
Step 4: Compiling the Design and Verifying Debug Nodes
Step 5: Programming the Device and Verifying the Hardware
Step 6: Verifying Hardware with Signal Tap

3.1. Step 1: Adding Files and Running Synthesis

Incorporate the black-box file to the Consumer project.

Open the a10_pcie_devkit_design_block_reuse_stp/Core_Partition_Reuse/Consumer/top.qpf project file.
Click Project > Add/Remove Files in Project.
On the Files pane, click the browse (...) button next to the File name field to locate and select the /Core_Partition_Reuse/Consumer/blinking_led_top_bb.sv black box file.
Click Open, and then click OK.
The file is now a source file in the project.
On the Compilation Dashboard, click Analysis & Synthesis to synthesize the design. When synthesis is complete, the Compilation Dashboard displays a check mark.

3.2. Step 2: Creating a Signal Tap File

Create a Signal Tap file that includes partition boundary ports from the reused core partition.

Click Tools > Signal Tap Logic Analyzer.
In the Signal Tap logic analyzer GUI, click auto_signaltap_0.
In the Setup tab, double-click to launch the Node Finder.
In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.

Figure 27. Node Finder Search

The Matching Nodes list shows signals that match the search criteria.
Add the boundary ports from the imported partition (db_*) from u_blinking_led_top to the Nodes Found list.

The names must match what appears in the Developer project's report file.

Figure 28. Node Finder

Note: If you add nodes other than the db_* nodes from the imported partition, the Compiler leaves them unconnected.
Add nodes count[2:0] from the root partition to the Nodes Found list, and click Insert.

Figure 29. Node Finder Copy Nodes
Configure the Signal Tap acquisition. Refer to Step 6: Creating a Signal Tap File (Optional) for details.

Figure 30. Specifying the Clock Source
Click File > Save, and save the file as stp_core_partition_reuse.stp.
A dialog box appears asking if you want to enable Signal Tap file for the project.
Click Yes, and close the file.

3.3. Step 3: Creating a Partition for blinking_led_top

Create a new partition and assign the .qdb file from the Developer project to the partition.

In the Project Navigator, right-click the u_blinking_led_top instance in the Hierarchy tab, and then click Design Partition > Default. A design partition icon appears next to each instance you assign.

Figure 31. Create Design Partition

Note: If the Design Partition Window is not visible on the GUI, click Assignments > Design Partitions Window.
Double-click in the Partition Database File cell for the u_blinking_led_top instance, and then click browse (...). Select the blinking_led_top.qdb file copied from the Developer project.

Figure 32. qdb Assignment in Design Partitions Window
Click the partition name blinking_led_top to deselect the Partition Database File column. This action confirms the .qdb file assignment.

3.4. Step 4: Compiling the Design and Verifying Debug Nodes

After creating Signal Tap files for the parent and blinking_led_top partitions, you are ready to run a full compilation of the design. Then, verify the debug nodes connection.

Click Compile Design on the Compilation Dashboard.
In the Compilation Report, under Synthesis, view the In-System Debugging > Connections to In-System Debugging Instance “auto_signaltap_0” report to verify the connection of the ports.

In the report, the Status column shows the connected debug ports.

3.5. Step 5: Programming the Device and Verifying the Hardware

You can now verify the results of the Core Partition Reuse—Consumer tutorial module on the hardware.

Program the device, as Step 7: Programming the Device and Verifying the Hardware describes.
After programming is complete, verify the following:
- LEDs AC6 and AE6 map to blinking_led_top.
- LEDs AC7 and AF6 map to top-level design.
After configuring the FPGA, the blinking_led_top core flashes LEDs in binary order. The top-level design shows a shifting bit in green.

3.6. Step 6: Verifying Hardware with Signal Tap

In the Signal Tap window, click File > Open, and open stp_core_partition_reuse.stp.
Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
Set up the JTAG Chain Configuration, and ensure Instance Manager is Ready to acquire.
As trigger condition, select db_count_24, right click the column under Trigger Conditions, and set to Falling Edge.
Run analysis by clicking Processing > Run Analysis.
When the analysis finishes, the Waveform tab shows the captured data.

Figure 33. Captured Data in Waveform Tab

db_value_0 and db_count_24 signals behaves identically to the Developer flow tutorial.
The db_value_0 changes as per db_count_24 a cycle later.
The db_value_* and db_count_* are the partition boundary ports from the imported partition.
db_count_0, db_count_1 and db_count_2 signals show the transition of the counter inside the imported partition.
The count[0], count[1], count[2] signals show the transition of another counter in the parent partition during this process.

4. Root Partition Reuse Debug—Developer

Process Description

The Developer adds bridge components to enable debug of the reserved core partition, and adds a Signal Tap HDL instance to debug the root partition. Then, the Developer compiles and exports the root partition, including logic and periphery resources, and finally, copies the root_partition .qdb and .sdc files to the Consumer project.

Completed Tutorial Files

In the a10_pcie_devkit_design_block_reuse_stp folder, the Root_Partition_Reuse/Completed/Developer/ directory contains the completed files for this tutorial module.

Steps

This tutorial module includes the following steps:

Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region
Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition
Step 3: Generating and Instantiating the SLD JTAG Bridge Host
Step 4: Generating HDL Instance of Signal Tap
Step 5: Compiling Export Root Partition and Copying Files to Consumer Project
Step 6: Programming the Device and Verifying the Hardware
Step 7: Generating a Signal Tap File for the Root Partition
Step 8: Verifying the Hardware with Signal Tap

4.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project, and open the a10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Developer/top.qpf project file.
On the Compilation Dashboard, click Analysis & Synthesis to synthesize the design. When synthesis is complete, the Compilation Dashboard displays a check mark.
In the Project Navigator, right-click the u_blinking_led_top instance in the Hierarchy tab, and then click Design Partition > Reserved Core. A design partition icon appears next to each instance you assign.

Note: If the Design Partition Window is not visible on the GUI, click Assignments > Design Partitions Window.

Figure 34. Set Reserved Core Partition Type
Right-click the u_blinking_led_top instance in the Project Navigator, and click Logic Lock Region > Create New Logic Lock Region.
To modify the region properties, click Assignments > Logic Lock Regions Window.
Change the Width to 123, and the Height to 61.
In the Origin column, specify X63_Y102.
Enable the Reserved and Core-Only options.
In the Size/State column, specify Fixed/Locked.
Click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.
Specify Fixed with expansion with Expansion Length of 0 for the Routing Type. The actual size and location are arbitrary for this tutorial. However, you can view and adjust the Logic Lock Region shape in the Chip Planner.

Figure 35. Logic Lock Regions Window

4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition

From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Agent Intel^® FPGA IP . Set the name as debug_agent.
For details about generating the SLD JTAG Bridge Agent Intel^® FPGA IP, refer to the Intel^® Quartus^® Prime Pro Edition User Guide: Debug Tools .

Open the top.sv file, uncomment lines 56 to 65 and 74 to 79, and save the file.

This action instantiates the SLD JTAG Bridge Agent in the root partition.

Lines 56 to 65:

//   wire tck, tms, tdi, vir tdi, ena, tdo; 
//   debug_agent debug_agent_inst ( 
//      .tck (tck), //output, width=1, connect_to_bridge_host .tck
//      .tms (tms), //output, width=1,        .tms
//      .tdi (tdi), //output, width=1,        .tdi
//      .vir_tdi (vir_tdi),//output, width=1, .vir_tdi
//      .ena (ena),  //output, width=1,       .ena
//      .tdo (tdo)   // input, width=1,       .tdo
//      );

Lines 74 to 79:

//   .tck (tck),   //input,  width=1, connect_to_bridge_host .tck
//   .tms (tms),   //input,  width=1,        .tms
//   .tdi (tdi),   //input,  width=1,        .tdi
//   .vir_tdi (vir_tdi), //input,  width=1,  .vir_tdi
//   .ena (ena),      //input,  width=1,     .ena
//   .tdo (tdo)      //output, width=1,      .tdo

4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host

From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Host Intel^® FPGA IP . Set the name as debug_host.
For details about generating the SLD JTAG Bridge Host Intel^® FPGA IP, refer to the Intel^® Quartus^® Prime Pro Edition User Guide: Debug Tools .

Open the blinking_led_top.sv file, uncomment the lines 25 to 30 and 41 to 48, and save the file.

This action instantiates the SLD JTAG Bridge Host in the Reserved Core partition, connecting the debug fabric to the parent partition.

Lines 25 to 30:

//		input wire tck (tck),		 // connect_to_bridge_host .tck
//		input wire tms (tms),		 // .tms
//		input wire tdi (tdi),	 	// .tdi
//		input wire vir_tdi (vir_tdi), // .vir_tdi
//		input wire ena (ena),		 // .ena
//		output wire tdo (tdo)		 // .tdo

Lines 41 to 48:

//   debug_host debug_host_inst ( 
//      .tck (tck),   //input, width=1, connect_to_bridge_host .tck
//      .tms (tms),   //input, width=1, .tms
//      .tdi (tdi),   //input, width=1, .tdi
//      .vir_tdi (vir_tdi), //input, width=1, .vir_tdi
//      .ena (ena),    //input, width=1, .ena
//      .tdo ()        //output, width=1, .tdo
//      );

4.4. Step 4: Generating HDL Instance of Signal Tap

From the IP Catalog (Tools > IP Catalog), select and double-click the Signal Tap Logic Analyzer Intel^® FPGA IP . Set the name as stp_root_partition.
In the IP Parameter Editor, change Data Input Port Width to 8 and Trigger Input Port Width to 8.

Figure 36. Signal Tap Logic Analyzer Intel^® FPGA IP Parameter Editor
Generate the IP.

In the top.sv file, uncomment lines 45 to 49, and save the file.

This action instantiates the HDL Signal Tap logic analyzer in the root partition.

Lines 45 to 49:

// stp_root_partition stp_root_partition inst (
//   .acq_clk (clock),// input, width=1, acq_clk.clk
//   .acq_data_in \
//      ({top_LED, count[3:0]}),// input, width=4, tap.acq_data_in
//   .acq_trigger_in \
//      ({top_LED, count[3:0]})// input, width=4, tap.acq_trigger_in
//   );

4.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project

When you export the root partition, you include all resources outside of the reserved core partition. The logic inside the reserved core, including the SLD JTAG Bridge Host, are not exported.

Click Compile Design on the Compilation Dashboard.
To export the root partition to a .qdb file, click Project > Export Design Partition. Select root_partition for the Partition name, final for Snapshot and turn on Include entity-bound SDC files for the selected partition:

Figure 37. Export Design Partition
Copy the root_partition.qdb and top.sdc files to the Root_Partition_Reuse/Consumer/ directory.
When you include entity bound .sdc files with the partition export, you need to only copy the top-level .sdc file, which is not bound to an entity. The top-level design uses constraints for analysis only, and does not drive any logic or routing.

When reusing the root partition, the Consumer integrates the root_partition.qdb and top.sdc files into the Consumer project. The Consumer can also include a separate .sdc file to constrain the logic that they use in the reserved core partition.

The Logic Lock (Standard) boundary is visible in the Chip Planner in the Consumer project for reference only. The Consumer cannot modify this region.

4.6. Step 6: Programming the Device and Verifying the Hardware

Program the device, as Step 7: Programming the Device and Verifying the Hardware describes.
After programming is complete, verify the following:
- LEDs AC6 and AE6 map to blinking_led_top.
- LEDs AC7 and AF6 map to top-level design.
When you create and load the .sof, the blinking_led_top core does not illuminate any LEDs. The top-level design shows a shifting bit in green. The behavior of the periphery LED driver carries into the Consumer project via the final .qdb file.

4.7. Step 7: Generating a Signal Tap File for the Root Partition

Go to the shell from where you opened the Intel^® Quartus^® Prime software.
In the shell, go to directory a10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Developer, and then run the following command:
```
quartus_stp top --create_signaltap_hdl_file --stp_file \
stp_root_partition.stp
```

4.8. Step 8: Verifying the Hardware with Signal Tap

In the Signal Tap window, click File > Open, and open the stp_root_partition.stp file, which you created in the previous step.
Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
Set up the JTAG Chain Configuration, and ensure Instance Manager is Ready to acquire.
Verify that Bridge Index is set to None Detected in the JTAG Chain Configuration window.

Figure 38. JTAG Chain Configuration
To set the trigger condition, select the count[0], count[1], count[2], and count[3] signals, right-click the column under Trigger Conditions, and select Falling Edge.

Figure 39. Trigger Conditions
Run analysis by clicking Processing > Run Analysis.
When the analysis finishes, the Waveform tab shows the captured data.
Verify the transition of the nodes in the root partition.

Figure 40. Waveforms for Root Partition Nodes in Developer Project

In this tutorial design, the count[3:0] signals represent the counter in the root partition, and the top_LED signals represent the green LEDs on the board, which also map to the top-level (root) design. After the trigger activates, only one of the top_LED bits is low, at any time.

If the root partition reuse succeeds, the Consumer project must present an identical behavior to the Developer project, since the Consumer imports the root partition .qdb file from this Developer project.

5. Root Partition Reuse Debug—Consumer

Process Description

The root partition Consumer receives from the Developer the final top-level, placed, and routed root partition, and optionally a .sdc file. Then, the Consumer enables the reserved core partition for debug by instantiating the SLD JTAG Bridge Host, which communicates with the SLD JTAG Bridge Agent instantiated in the root partition. Finally, the Consumer taps pre-synthesis nodes in the Signal Tap GUI to debug the reserved core partition.

Completed Tutorial Files

The Root_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Step 1: Adding Files to Customer Project
Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition
Step 3: Synthesizing, Creating Signal Tap File, and Compiling
Step 4: Programming the Device and Verifying the Hardware
Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap
Step 6: Verifying Hardware of Root Partition with Signal Tap

5.1. Step 1: Adding Files to Customer Project

You import the timing constraints and the root partition database from the Developer project.

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project, and open the a10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Consumer/top.qpf project file.
Click Project > Add/Remove Files in Project.
On the Files pane, click the browse (...) button next to the File name field to locate and select the top.sdc file, and click Add.
Click Apply, and then click OK.
If the Design Partitions Window is not visible, click Assignments > Design Partitions Window.
In the Design Partitions Window, locate the root partition row, double-click the Partition Database File field, and then click browse (...).
Select the root_partition.qdb file copied over from the Developer project.
Click the partition name to confirm the .qdb assignment.

5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition

Exporting the root partition in the Developer project does not include logic inside the reserved core or the SLD JTAG Bridge Host. The Consumer must add the SLD JTAG Bridge Host to the reserved core in the Consumer project.

From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Host Intel^® FPGA IP . Set the name as debug_host.
Open the blinking_led_top.sv file, uncomment lines 26 to 31 and 48 to 55, and save the file.

5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling

On the Compilation Dashboard, click Analysis & Synthesis to synthesize the design. When synthesis is complete, the Compilation Dashboard displays a check mark.
In the Project Navigator, right-click the u_blinking_led_top instance in the Hierarchy tab, and then click Design Partition > Default.

Important: root_partition.qdb contains the information about u_blinking_led_top from Developer project. It is not necessary to set the partition type to Reserved Core and create the Logic Lock Region for it.
In the Intel^® Quartus^® Prime Pro Edition software, click Tools > Signal Tap Logic Analyzer.
In the Instance Manager, click auto_signaltap_0.
In the Setup tab, double-click to launch the Node Finder.
In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.
In the Matching Nodes list, expand the u_blinking_led_top|count.
Select count[0], count[1], count[2], and count[24]. Insert the nodes by clicking >.
Select value_top under u_blinking_led_top. Click >, then click Insert, and then click Close.
In the Signal Tap window, under Signal Configuration, click (…) next to the Clock field.
In the Node Finder, search for *, and select the clock node in the reserved core partition u_blinking_led_top. Click >, and then click OK to close.
Leave all the other options as default under Signal Configuration. Go to File > Save and save the file as stp_periphery_reuse_core.stp.
A dialog box appears asking if you want to enable Signal Tap file for the project.
Click Yes, and close the file.
Click Compile Design on the Compilation Dashboard.

5.4. Step 4: Programming the Device and Verifying the Hardware

Program the device, as Step 7: Programming the Device and Verifying the Hardware describes.
After programming is complete, verify the following:
- LEDs AC6 and AE6 map to blinking_led_top
- LEDs AC7 and AF6 map to top-level design.
After configuring the FPGA, the blinking_led_top core flashes LEDs in a binary counting order. The top-level design shows a single bit shifting in green.

5.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap

To use Signal Tap GUI for the reserved core:

Determine the bridge index according to the number in the synthesis report file (Root_Partition_Reuse/Developer/output_files/top.syn.rpt), under JTAG Bridge Agent Instance Information in the Developer project.

Figure 41. Synthesis Report
In the Signal Tap window, click File > Open, and open stp_periphery_reuse_core.stp.
Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
Set up the JTAG Chain Configuration, and ensure Instance Manager is Ready to acquire.
Set the Bridge Index as found in the synthesis report (Root_Partition_Reuse/Developer/output_files/top.syn.rpt in the Developer Project
If the values for Bridge Index are different, Signal Tap reports Instance not found.
Figure 42. Setting the Bridge Index
To set the trigger condition, select count[24], right click the column under Trigger Conditions and select Falling Edge.

Figure 43. Trigger Conditions
Run analysis by clicking Processing > Run Analysis.
When the analysis finishes, the Waveform tab shows the captured data.
Verify the transition of reserved core nodes in Signal Tap GUI. The expected behavior is:
- value_top[0] transitions along with count[24].
- count[0], count[1], and count[2] show the transition of other counter bits in the reserved core partition during this process.
Figure 44. Waveforms for reserved core Partition Nodes in Consumer Project

5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap

Go to the shell from where you opened the Intel^® Quartus^® Prime software.
In the shell, go to directory a10_pcie_devkit_design_block_reuse_stp/Root_Partition_Reuse/Consumer , and then run the following command:
```
quartus_stp top --create_signaltap_hdl_file --stp_file \
stp_root_partition.stp
```
In the Signal Tap window, click File > Open, and open the stp_root_partition.stp file, which you created in the previous step.
Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
Verify that Bridge Index is set to None in the JTAG Chain Configuration window
To set the trigger condition, select the count[0], count[1], count[2], and count[3] signals, right-click the column under Trigger Conditions, and select Falling Edge.
Run analysis by clicking Processing > Run Analysis.
When the analysis finishes, the Waveform tab shows the captured data.
Verify the transition of the nodes in the root partition.

Figure 45. Waveforms for Root Partition Nodes in Consumer Project

If the implementation succeeds, the Consumer project behaves identically to the Developer project.

6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel Arria 10 FPGA Development Board Archives

If the table does not list a software version, the user guide for the previous software version applies.

Intel^® Quartus^® Prime Version	User Guide
19.3	AN 847: Signal Tap Tutorial with Design Block Reuse for Intel Arria 10 FPGA Development Board
19.1	AN 847: Signal Tap Tutorial with Design Block Reuse for Intel Arria 10 FPGA Development Board
18.0	AN 847: Signal Tap Tutorial with Design Block Reuse for Intel Arria 10 FPGA Development Board

7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel Arria 10 FPGA Development Board

Document Version	Intel^® Quartus^® Prime Version	Changes
2020.12.21	20.3	Updated the design example in Tutorial Files. In Step 2: Creating Partition Boundary Ports, updated step 5 with additional information. In Step 6: Creating a Signal Tap File, made minor corrections in step 5.
2019.12.11	19.3	In Introduction, added Core Partition Reuse Example. Updated Step 7: Programming the Device and Verifying the Hardware topic completely to include more steps about how to program the device. In Step 8: Verifying Hardware with Signal Tap , updated the Waveform after Signal Tap Analysis image. In Step 5: Programming the Device and Verifying the Hardware, updated step 2 LEDs. In Step 6: Verifying Hardware with Signal Tap , updated the Captured Data in Waveform Tab image. In Step 8: Verifying the Hardware with Signal Tap , updated the Waveforms for Root Partition Nodes in Developer Project image. image. In Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region, updated step 6 and 7 values. In Step 4: Generating HDL Instance of Signal Tap, updated the image Signal Tap Logic Analyzer Intel FPGA IP Parameter Editor. In Step 6: Programming the Device and Verifying the Hardware, updated step 2 LEDs. In Step 4: Programming the Device and Verifying the Hardware, updated step 2 LEDs. In Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap , updated the Waveforms for reserved core Partition Nodes in Consumer Project image. In Step 6: Verifying Hardware of Root Partition with Signal Tap , updated the Waveforms for Root Partition Nodes in Consumer Project.
2019.09.11	19.1	Minor bug fix in Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition and Step 3: Generating and Instantiating the SLD JTAG Bridge Host topics.
2019.06.11	19.1	All occurrences of 'Periphery Reuse Core' partitions changed to 'Reserved Core' partitions. Changed the convention of Intel^® Quartus^® Prime user guide titles. Removed all inline icons and replaced it with menu options where applicable. Updated all waveform images. In Step 1: Creating a Core Partition, changed 'Set as Design Partition' to ' Default' and added note. Associated image was also updated. Updated Step 4: Exporting the Core Partition and Creating the Black Box File to map to the GUI. In Step 3: Creating a Partition for blinking_led_top, updated steps 1 and 2 images. Also changed 'Set as Design Partition' to ' Default' and added a note in step 1. In Step 1: Creating a Reserved Core Partition and Defining a Region, updated step 3 to use Reserved Core design partition type. Updated the relevant image and removed the step about setting the core partition type. In Step 3: Synthesizing, Creating File, and Compiling, added a new step 2 and an important note. Updated the design example.
2018.05.07	18.0.0	Initial release.