AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

4. Root Partition Reuse Debug—Developer

Process Description

The Developer adds bridge components to enable debug of the reserved core partition, and adds a Signal Tap HDL instance to debug the root partition. Then, the Developer compiles and exports the root partition, including logic and periphery resources, and finally, copies the root_partition .qdb and .sdc files to the Consumer project.

Completed Tutorial Files

In the a10_pcie_devkit_design_block_reuse_stp folder, the Root_Partition_Reuse/Completed/Developer/ directory contains the completed files for this tutorial module.