AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

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ID 683712
Date 12/21/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Core Partition Reuse Debug—Developer 3. Core Partition Reuse Debug—Consumer 4. Root Partition Reuse Debug—Developer 5. Root Partition Reuse Debug—Consumer 6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives 7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board
1. Introduction x
1.1. Tutorial Software and Hardware 1.2. Tutorial Files 1.3. Signal Tap with Core Partition Reuse 1.4. Signal Tap with Root Partition Reuse
2. Core Partition Reuse Debug—Developer x
2.1. Step 1: Creating a Core Partition 2.2. Step 2: Creating Partition Boundary Ports 2.3. Step 3: Compiling and Checking Debug Nodes 2.4. Step 4: Exporting the Core Partition and Creating the Black Box File 2.5. Step 5: Copying Files to Consumer Project 2.6. Step 6: Creating a Signal Tap File (Optional) 2.7. Step 7: Programming the Device and Verifying the Hardware 2.8. Step 8: Verifying Hardware with Signal Tap
3. Core Partition Reuse Debug—Consumer x
3.1. Step 1: Adding Files and Running Synthesis 3.2. Step 2: Creating a Signal Tap File 3.3. Step 3: Creating a Partition for blinking_led_top 3.4. Step 4: Compiling the Design and Verifying Debug Nodes 3.5. Step 5: Programming the Device and Verifying the Hardware 3.6. Step 6: Verifying Hardware with Signal Tap
4. Root Partition Reuse Debug—Developer x
4.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region 4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition 4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host 4.4. Step 4: Generating HDL Instance of Signal Tap 4.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project 4.6. Step 6: Programming the Device and Verifying the Hardware 4.7. Step 7: Generating a Signal Tap File for the Root Partition 4.8. Step 8: Verifying the Hardware with Signal Tap
5. Root Partition Reuse Debug—Consumer x
5.1. Step 1: Adding Files to Customer Project 5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition 5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling 5.4. Step 4: Programming the Device and Verifying the Hardware 5.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap 5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap
1. Introduction
2. Core Partition Reuse Debug—Developer
3. Core Partition Reuse Debug—Consumer
4. Root Partition Reuse Debug—Developer
5. Root Partition Reuse Debug—Consumer
6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives
7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board

2.7. Step 7: Programming the Device and Verifying the Hardware

  1. To open the Intel® Quartus® Prime Programmer, click Tools > Programmer.
  2. Connect the board cables:
    • JTAG USB cable to board
    • Power cable attached to board and power source
  3. Turn on power to the board.
  4. In the Intel® Quartus® Prime Programmer, click Hardware Setup.
    Figure 18. Hardware Setup
  5. In the Hardware list, select USB-BlasterII, and then click Close. The device chain appears.
    Note: If the device chain does not appear, verify the board connections.
  6. Click Auto-Detect. The device chain populates.
  7. In the Found Devices list, select the device that matches your design and click OK. For this tutorial, select the 10AX115S2 device that matches the 10AX115S2F45I1SG FPGA on the Intel® Arria® 10 GX Development Kit.
    Figure 19. Select Device
  8. Right-click the 10AX115S2 row in the file list, and then click Change File.
    Figure 20. Programmer Window
  9. Browse to select the top.sof file from the appropriate tutorial/output_files/ directory.
  10. Enable the Program/Configure option for the 10AX115S2 row.
    Figure 21. Program/Configure Option
  11. Click Start. The progress bar reaches 100% when device configuration is complete. The device is now fully configured and in operation.
    Figure 22. Programming Successful
    Note: If device configuration fails, make sure the device you select for configuration matches the device you specify during .sof file generation.
  12. Verify the LEDs behavior.
After completing this tutorial module:
  • LEDs AC6 and AE6 map to blinking_led_top.
  • LEDs AC7 and AF6 map to top-level design.

The blinking_led_top core flashes LEDs in binary order, and the top-level design does not illuminate any LEDs.

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