AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

2.6. Step 6: Creating a Signal Tap File (Optional)

In this step, you configure the Signal Tap logic analyzer, and then tap partition boundary ports and pre-synthesis nodes from the parent partition to debug in the Developer project. Configuring the Signal Tap logic analyzer includes adding a reference clock and specifying acquisition settings.
  1. In the Intel® Quartus® Prime Pro Edition software, click Tools > Signal Tap Logic Analyzer.
    Figure 15.  Signal Tap Logic Analyzer Window
  2. In the Instance Manager, click auto_signaltap_0.
  3. In the Setup tab, double-click to launch the Node Finder.
  4. In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.
  5. In the Matching Nodes list, expand u_blinking_led_top. Select db_value_0, db_value_1, db_value_2, and db_value_3.
    Figure 16. Node Finder Copy Nodes
  6. In the Matching Nodes list, expand the u_blinking_led_top > u_counter > count_int.
  7. From the node list, select count_int[0], count_int[1], count_int[2], and count_int[24], and insert the nodes by clicking >.
  8. Click Insert, and then Close.
  9. In the Signal Tap window, under Signal Configuration, click () next to the Clock field.
  10. In the Node Finder, search for *, and select the clock.
  11. Click >, and then click OK to close.
    Figure 17. Clock Signal in Node Finder
  12. Leave all other options as default under Signal Configuration.
  13. Go to File > Save and save the file as stp_core_partition_reuse.stp.
    A dialog box appears asking if you want to enable Signal Tap file for the project.
  14. Click Yes, and close the file.
  15. Click Compile Design on the Compilation Dashboard.

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