AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Public
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3.2. Step 2: Creating a Signal Tap File

Create a Signal Tap file that includes partition boundary ports from the reused core partition.
  1. Click Tools > Signal Tap Logic Analyzer.
  2. In the Signal Tap logic analyzer GUI, click auto_signaltap_0.
  3. In the Setup tab, double-click to launch the Node Finder.
  4. In the Node Finder, type * in the Named field, set Filter to Signal Tap: pre-synthesis, and then click Search.
    Figure 27. Node Finder Search
    The Matching Nodes list shows signals that match the search criteria.
  5. Add the boundary ports from the imported partition (db_*) from u_blinking_led_top to the Nodes Found list.

    The names must match what appears in the Developer project's report file.

    Figure 28. Node Finder
    Note: If you add nodes other than the db_* nodes from the imported partition, the Compiler leaves them unconnected.
  6. Add nodes count[2:0] from the root partition to the Nodes Found list, and click Insert.
    Figure 29. Node Finder Copy Nodes
  7. Configure the Signal Tap acquisition. Refer to Step 6: Creating a Signal Tap File (Optional) for details.
    Figure 30. Specifying the Clock Source
  8. Click File > Save, and save the file as stp_core_partition_reuse.stp.
    A dialog box appears asking if you want to enable Signal Tap file for the project.
  9. Click Yes, and close the file.