AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

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ID 683712
Date 12/21/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Core Partition Reuse Debug—Developer 3. Core Partition Reuse Debug—Consumer 4. Root Partition Reuse Debug—Developer 5. Root Partition Reuse Debug—Consumer 6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives 7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board
1. Introduction x
1.1. Tutorial Software and Hardware 1.2. Tutorial Files 1.3. Signal Tap with Core Partition Reuse 1.4. Signal Tap with Root Partition Reuse
2. Core Partition Reuse Debug—Developer x
2.1. Step 1: Creating a Core Partition 2.2. Step 2: Creating Partition Boundary Ports 2.3. Step 3: Compiling and Checking Debug Nodes 2.4. Step 4: Exporting the Core Partition and Creating the Black Box File 2.5. Step 5: Copying Files to Consumer Project 2.6. Step 6: Creating a Signal Tap File (Optional) 2.7. Step 7: Programming the Device and Verifying the Hardware 2.8. Step 8: Verifying Hardware with Signal Tap
3. Core Partition Reuse Debug—Consumer x
3.1. Step 1: Adding Files and Running Synthesis 3.2. Step 2: Creating a Signal Tap File 3.3. Step 3: Creating a Partition for blinking_led_top 3.4. Step 4: Compiling the Design and Verifying Debug Nodes 3.5. Step 5: Programming the Device and Verifying the Hardware 3.6. Step 6: Verifying Hardware with Signal Tap
4. Root Partition Reuse Debug—Developer x
4.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region 4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition 4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host 4.4. Step 4: Generating HDL Instance of Signal Tap 4.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project 4.6. Step 6: Programming the Device and Verifying the Hardware 4.7. Step 7: Generating a Signal Tap File for the Root Partition 4.8. Step 8: Verifying the Hardware with Signal Tap
5. Root Partition Reuse Debug—Consumer x
5.1. Step 1: Adding Files to Customer Project 5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition 5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling 5.4. Step 4: Programming the Device and Verifying the Hardware 5.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap 5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap
1. Introduction
2. Core Partition Reuse Debug—Developer
3. Core Partition Reuse Debug—Consumer
4. Root Partition Reuse Debug—Developer
5. Root Partition Reuse Debug—Consumer
6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives
7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board

1.4. Signal Tap with Root Partition Reuse

In a root partition reuse flow, the Developer extends the debug fabric into the Reserved Core partition with a debug bridge. The debug bridge also allows debugging of the reserved core partition in the Consumer project. The components of a debug bridge are:
  • SLD JTAG Bridge Agent Intel® FPGA IP : Instantiate in the higher-level partition to connect to an SLD JTAG Bridge Host in the child partition.
  • SLD JTAG Bridge Host Intel® FPGA IP : Instantiate in the child partition to connect to an SLD JTAG Bridge Agent in the higher-level partition.
With the bridge in place, the Developer adds the Signal Tap logic analyzer to the root partition with either of the following methods:
  • Signal Tap HDL instance
  • Signal Tap GUI to tap pre-synthesis or post-fit nodes

The Intel® Quartus® Prime Pro Edition software supports multiple instances of bridge components in partitions and their children. The Compiler assigns an index number to distinguish each instance. The bridge index for the root partition is always None. You can view the bridge index for child partitions in the synthesis report, under JTAG Bridge Agent Instance Information.

Each instance of the Signal Tap logic analyzer can only connect within the partition that the instance resides. Therefore, the root partition and reserved core partition require separate Signal Tap files in this flow.

The Consumer must instantiate the SLD JTAG Bridge Host in the reserved core partition, and add Signal Tap to the reserved core partition with either of the following methods:
  • Signal Tap HDL instance
  • Signal Tap GUI to tap pre-synthesis or post-fit nodes
Figure 5. Debug Setup with Reused Root Partition
In this root partition reuse tutorial, the Developer adds an HDL instance of the Signal Tap logic analyzer to debug the root partition, and adds bridge components to enable debug of the reserved core partition. Then, in the Consumer project, the Consumer adds the SLD JTAG Bridge Host to enable debug of the reserved core partition, and uses the Signal Tap GUI to tap pre-synthesis nodes.
Figure 6. Tutorial Design Flow for Root Partition Reuse
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