AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

ID 683712
Date 12/21/2020
Document Table of Contents

4.8. Step 8: Verifying the Hardware with Signal Tap

  1. In the Signal Tap window, click File > Open, and open the stp_root_partition.stp file, which you created in the previous step.
  2. Ensure that the development kit is powered ON and connected to the machine from which you open the Signal Tap logic analyzer.
  3. Set up the JTAG Chain Configuration, and ensure Instance Manager is Ready to acquire.
  4. Verify that Bridge Index is set to None Detected in the JTAG Chain Configuration window.
    Figure 38. JTAG Chain Configuration
  5. To set the trigger condition, select the count[0], count[1], count[2], and count[3] signals, right-click the column under Trigger Conditions, and select Falling Edge.
    Figure 39. Trigger Conditions
  6. Run analysis by clicking Processing > Run Analysis.
    When the analysis finishes, the Waveform tab shows the captured data.
  7. Verify the transition of the nodes in the root partition.
    Figure 40. Waveforms for Root Partition Nodes in Developer Project

In this tutorial design, the count[3:0] signals represent the counter in the root partition, and the top_LED signals represent the green LEDs on the board, which also map to the top-level (root) design. After the trigger activates, only one of the top_LED bits is low, at any time.

If the root partition reuse succeeds, the Consumer project must present an identical behavior to the Developer project, since the Consumer imports the root partition .qdb file from this Developer project.